VersaClock® Programmable
Clock Generator
5P35023
Datasheet
Description
Features
▪ Configurable OE pin function as OE, PD#, PPS or DFC control
function
The 5P35023 is a VersaClock programmable clock generator and
is designed for low-power, consumer, and high-performance PCI
Express applications. The 5P35023 device is a three PLL
architecture design, and each PLL is individually programmable
and allowing for up to six unique frequency outputs.
▪ Configurable PLL bandwidth; minimizes jitter peaking
▪ PPS: Proactive Power Saving features save power during the
end device power down mode
The 5P35023 has built-in unique features such as Proactive
Power Saving (PPS), Performance-Power Balancing (PPB),
Overshot Reduction Technology (ORT) and Extreme Low Power
DCO. An internal OTP memory allows the user to store the
configuration in the device. After power up, the user can change
the device register settings through the I2C interface when I2C
mode is selected.
▪ PPB: Performance Power Balancing feature allows minimum
power consumption based on required performance
▪ DFC: Dynamic Frequency Control feature allows user to
dynamically switch between and up to 4 different frequencies
smoothly
▪ Two PLLs support independent spread spectrum clocks to
lower system EMI
The device has programmable VCO and PLL source selection to
allow the user to do power-performance optimization based on the
application requirements. It also supports three single-ended
outputs and two pair of differential outputs that support LVCMOS,
LVPECL, LVDS and LP-HCSL. A Low Power 32.768kHz clock is
supported with only less than 2µA current consumption for system
RTC reference clock.
▪ Store user configuration into OTP memory
▪ I2C interface
▪ Available in Automotive Grade 2 (-40°C to +105°C) or
industrial (-40° to +85°) temperature ranges
Output Features
▪ 2 DIFF outputs with configurable LP-HSCL, LVDS, LVPECL,
LVCMOS output pairs. 1MHz–500MHz (160MHz with LVCMOS
mode)
Typical Applications
▪ PCIe Gen1–3 clock generator
▪ 3 LVCMOS outputs: 1MHz–160MHz
▪ Consumer application crystal replacements
▪ SmartDevice, Handheld
▪ Maximum 8 LVCMOS outputs as REF + 3 × SE + 2 × DIFF_T/C
as LVCMOS
▪ Computing and consumer applications
▪ Low power 32.768kHz clock supported for all SE1–SE3
▪ Automotive applications (infotainment, dashboard,
camera/vision, computing, networking)
Key Specifications
▪ PCIe clocks phase jitter: PCIe Gen3
▪ Differential clocks < 1.5ps rms jitter integer range
12kHz–20MHz
©2016-2023 Renesas Electronics Corporation
1
November 22, 2023
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