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5P35023-000NLGI8 PDF预览

5P35023-000NLGI8

更新时间: 2024-10-28 01:03:51
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
34页 385K
描述
Programmable Clock Generator

5P35023-000NLGI8 数据手册

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VersaClock® Programmable Clock Generator  
5P35023  
DATASHEET  
General Description  
Features/Benefits  
The 5P35023 is a VersaClock programmable clock generator  
and is designed for low power, consumer, and  
high-performance PCI Express applications. The 5P35023  
device is a three PLL architecture design, and each PLL is  
individually programmable and allowing for up to six unique  
frequency outputs.  
Configurable OE pin function as OE, PD#, PPS or DFC  
control function  
Configurable PLL bandwidth/minimizes jitter peaking  
PPS: Proactive Power Saving features save power during  
the end device power down mode  
PPB: Performance- Power Balancing feature allows  
minimum power consumption base on required  
performance  
The 5P35023 has built-in unique features such as Proactive  
Power Saving (PPS), Performance-Power Balancing (PPB),  
Overshot Reduction Technology (ORT) and Extreme Low  
Power DCO. An internal OTP memory allows the user to store  
the configuration in the device. After power up, the user can  
change the device register settings through the I2C interface  
when I2C mode is selected.  
DFC: Dynamic Frequency Control feature allows user to  
dynamically switch between and up to 4 difference  
frequencies smoothly  
Two PLLs support independent Spread Spectrum clocks to  
lower system EMI  
Store user configuration into OTP memory  
I C interface  
2
The device has programmable VCO and PLL source selection  
to allow the user to do power-performance optimization based  
on the application requirements. It also supports three  
single-ended outputs and two pair of differential outputs that  
support LVCMOS, LVPECL, LVDS and LPHCSL. A Low  
Power 32.768kHz clock is supported with only less than 2µA  
current consumption for system RTC reference clock.  
Key Specifications  
PCIe clocks phase jitter: PCIe Gen3  
Differential clocks <3 ps rms jitter integer range  
12KHz~20MHz  
Output Features  
2 – DIFF outputs with configurable LPHSCL, LVDS,  
LVPECL, LVCMOS output pairs. 1MHz~500MHz (160MHz/  
with LVCMOS mode)  
Recommended Application  
PCIe Gen1/2/3 clock generator  
Consumer application crystal replacements  
SmartDevice, Handheld, Computing and Consumer  
applications  
3 – LVCMOS outputs; 1MHz~160MHz  
Maximum 8 LVCMOS outputs as REF + 3* SE +  
2*DIFF_T/C as LVCMOS  
Low Power 32.768kHz clock supported for all SE1~SE3  
Pin Assignment  
24  
23  
22  
21  
20  
19  
1
2
3
4
5
6
18  
17  
16  
15  
14  
13  
VDDA  
SDA_DFCO  
DIFF1  
DIFF1B  
VDDDIFF1  
OE1  
SEL_DFC/SCL_DFC1  
CLKIN/X2  
5P35023  
CLKINB/X1  
SE1  
VBAT  
VDDSE1  
7
8
9
10  
11  
12  
24-pin VFQFPN  
5P35023 JANUARY 25, 2017  
1
©2017 Integrated Device Technology, Inc.  

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