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5962-9758801Q2A PDF预览

5962-9758801Q2A

更新时间: 2024-01-07 15:38:21
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路输入元件
页数 文件大小 规格书
6页 92K
描述
QUADRUPLE 2-INPUT POSITIVE-OR GATES

5962-9758801Q2A 技术参数

生命周期:Active零件包装代码:QLCC
包装说明:QCCN, LCC20,.35SQ针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.35
系列:F/FASTJESD-30 代码:S-CQCC-N20
长度:8.89 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.001 A
功能数量:4输入次数:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):15.5 mA
Prop。Delay @ Nom-Sup:7.5 ns传播延迟(tpd):7.5 ns
认证状态:Qualified施密特触发器:NO
筛选级别:MIL-PRF-38535 Class Q座面最大高度:2.03 mm
子类别:Gate最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子形式:NO LEAD
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8.89 mm
Base Number Matches:1

5962-9758801Q2A 数据手册

 浏览型号5962-9758801Q2A的Datasheet PDF文件第2页浏览型号5962-9758801Q2A的Datasheet PDF文件第3页浏览型号5962-9758801Q2A的Datasheet PDF文件第4页浏览型号5962-9758801Q2A的Datasheet PDF文件第5页浏览型号5962-9758801Q2A的Datasheet PDF文件第6页 
SN54F32, SN74F32  
QUADRUPLE 2-INPUT POSITIVE-OR GATES  
SDFS044B – MARCH 1987 – REVISED MAY 1999  
SN54F32 . . . J PACKAGE  
SN74F32 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D) Packages, Ceramic Chip  
Carriers (FK), and Standard Plastic (N) and  
Ceramic (J) DIPs  
1A  
1B  
1Y  
2A  
2B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
4B  
4A  
4Y  
3B  
3A  
3Y  
description  
These devices contain four independent 2-input  
OR gates. They perform the Boolean functions  
Y = A + B or Y = A B in positive logic.  
2Y  
GND  
8
The SN54F32 is characterized for operation over  
the full military temperature range of –55°C to  
125°C. The SN74F32 is characterized for  
operation from 0°C to 70°C.  
SN54F32 . . . FK PACKAGE  
(TOP VIEW)  
FUNCTION TABLE  
(each gate)  
3
2 1 20 19  
18  
INPUTS  
OUTPUT  
Y
1Y  
NC  
2A  
4A  
17 NC  
4
5
6
7
8
A
B
X
H
L
H
X
L
H
H
L
16  
15  
14  
4Y  
NC  
3B  
NC  
2B  
9 10 11 12 13  
NC – No internal connection  
logic symbol  
1
1A  
2
3
1  
1Y  
1B  
4
6
2A  
5
2Y  
2B  
9
3A  
8
10  
3Y  
3B  
4A  
4B  
12  
13  
11  
4Y  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.  
Pin numbers shown are for the D, J, and N packages.  
logic diagram, each gate (positive logic)  
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1999, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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