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5962-9759201QCA PDF预览

5962-9759201QCA

更新时间: 2024-11-19 21:54:51
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
6页 100K
描述
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

5962-9759201QCA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP-14针数:14
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.02Is Samacsys:N
系列:F/FASTJESD-30 代码:R-GDIP-T14
长度:19.56 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:80000000 Hz
最大I(ol):0.02 A位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):16 mA
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):10.5 ns
认证状态:Qualified筛选级别:MIL-PRF-38535 Class Q
座面最大高度:5.08 mm子类别:FF/Latch
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:MILITARY
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.67 mm
最小 fmax:80 MHzBase Number Matches:1

5962-9759201QCA 数据手册

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SN54F74, SN74F74  
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH CLEAR AND PRESET  
SDFS046A – MARCH 1987 – REVISED OCTOBER 1993  
SN54F74 . . . J PACKAGE  
SN74F74 . . . D OR N PACKAGE  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
(TOP VIEW)  
1CLR  
1D  
1CLK  
1PRE  
1Q  
V
CC  
2CLR  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
description  
2D  
These devices contain two independent positive-  
edge-triggered D-type flip-flops. A low level at the  
preset (PRE) or clear (CLR) inputs sets or resets  
the outputs regardless of the levels of the other  
inputs. When PRE and CLR are inactive (high),  
data at the data (D) input meeting the setup time  
requirements is transferred to the outputs on the  
positive-going edge of the clock pulse. Clock  
triggering occurs at a voltage level and is not  
directly related to the rise time of the clock pulse.  
Following the hold-time interval, data at the  
D input may be changed without affecting the  
levels at the outputs.  
2CLK  
2PRE  
2Q  
1Q  
GND  
2Q  
8
SN54F74 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
1CLK  
NC  
2D  
17 NC  
4
5
6
7
8
16  
15  
14  
1PRE  
NC  
2CLK  
NC  
The SN54F74 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F74 is characterized for  
operation from 0°C to 70°C.  
1Q  
2PRE  
9 10 11 12 13  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
NC – No internal connection  
PRE  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
H
L
L
X
H
H
H
H
H
H
L
L
H
H
H
L
X
Q
Q
0
0
The output levels are not guaranteed to meet the  
minimum levels for Furthermore, this  
V
OH  
.
configuration is nonstable; that is, it will not persist  
when PRE or CLR returns to its inactive (high)  
level.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

5962-9759201QCA 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54F74J TI

完全替代

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN54F74J TI

完全替代

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
SN74ACT74N TI

类似代替

DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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