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5962-9759001QSA PDF预览

5962-9759001QSA

更新时间: 2024-01-10 04:26:40
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路输出元件
页数 文件大小 规格书
17页 690K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

5962-9759001QSA 技术参数

生命周期:Active零件包装代码:DFP
包装说明:DFP-20针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.17
Is Samacsys:N控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:F/FAST
JESD-30 代码:R-GDFP-F20长度:13.09 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:60000000 Hz最大I(ol):0.02 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL20,.3封装形状:RECTANGULAR
封装形式:FLATPACK包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):86 mAProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):11 ns认证状态:Qualified
筛选级别:MIL-PRF-38535 Class Q座面最大高度:2.45 mm
子类别:Bus Driver/Transceiver最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:6.92 mmBase Number Matches:1

5962-9759001QSA 数据手册

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ꢉ ꢊꢋꢌꢍꢈꢎ ꢏꢐ ꢎꢑꢋ ꢒꢓ ꢐꢐ ꢎꢒ ꢎꢏꢈ ꢏꢑꢋ ꢔꢕ ꢎꢈꢄ ꢍ ꢓꢕ ꢑ ꢄꢍꢉ ꢕ  
SDFS077A − D2932, MARCH 1987 − REVISED OCTOBER 1993  
SN54F374 . . . J PACKAGE  
SN74F374 . . . DB, DW, OR N PACKAGE  
(TOP VIEW)  
Eight D-Type Flip-Flops in a Single Package  
3-State Bus-Driving True Outputs  
Full Parallel Access for Loading  
Buffered Control Inputs  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
8Q  
8D  
7D  
7Q  
6Q  
6D  
Package Options Include Plastic  
Small-Outline (SOIC) and Shrink  
Small-Outline (SSOP) Packages, Ceramic  
Chip Carriers, and Plastic and Ceramic  
DIPs  
13 5D  
12 5Q  
description  
These 8-bit flip-flops feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. They are  
particularly suitable for implementing buffer  
registers, I/O ports, bidirectional bus drivers, and  
working registers.  
11  
GND  
CLK  
SN54F374 . . . FK PACKAGE  
(TOP VIEW)  
The eight flip-flops of the F374 are edge-triggered  
D-type flip-flops. On the positive transition of the  
clock (CLK) input, the Q outputs are set to the logic  
levels that were set up at the data (D) inputs.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
A buffered output enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or a high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and the increased drive  
provide the capability to drive bus lines without  
need for interface or pullup components.  
14 6D  
9 10 11 12 13  
The output enable (OE) input does not affect internal operations of the flip-flop. Old data can be retained or new  
data can be entered while the outputs are in the high-impedance state.  
The SN74F374 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54F374 is characterized for operation over the full military temperature range of 55°C to 125°C. The  
SN74F374 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each flip-flop)  
INPUTS  
OUTPUT  
Q
OE  
L
CLK  
D
H
L
H
L
L
L
H or L  
X
X
X
Q
0
H
Z
ꢋꢤ  
Copyright 1993, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
2−1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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