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5962-9758001QEA PDF预览

5962-9758001QEA

更新时间: 2024-11-26 05:05:43
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路
页数 文件大小 规格书
6页 98K
描述
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

5962-9758001QEA 技术参数

生命周期:Active零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.24
Is Samacsys:N系列:F/FAST
JESD-30 代码:R-GDIP-T16长度:19.56 mm
负载电容(CL):50 pF逻辑集成电路类型:J-KBAR FLIP-FLOP
最大频率@ Nom-Sup:70000000 Hz最大I(ol):0.02 A
位数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:TUBE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):17 mAProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):10.5 ns认证状态:Qualified
筛选级别:MIL-PRF-38535 Class Q座面最大高度:5.08 mm
子类别:FF/Latch最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:70 MHz
Base Number Matches:1

5962-9758001QEA 数据手册

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SN54F109, SN74F109  
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS  
WITH CLEAR AND PRESET  
SDFS047A – MARCH 1987 – REVISED OCTOBER 1993  
SN54F109 . . . J PACKAGE  
SN74F109 . . . D OR N PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline Packages, Ceramic Chip  
Carriers, and Standard Plastic and Ceramic  
300-mil DIPs  
1CLR  
1J  
VCC  
2CLR  
2J  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
description  
1K  
These devices contain two independent J-K  
positive-edge-triggered flip-flops. A low level at  
the preset (PRE) or clear (CLR) inputs sets or  
resets the outputs regardless of the levels of the  
other inputs. When PRE and CLR are inactive  
(high), data at the J and K input meeting the  
setup-time requirements are transferred to the  
outputs on the positive-going edge of the clock  
pulse. Clock triggering occurs at a voltage level  
and is not directly related to the rise time of the  
clock pulse. Following the hold time interval, data  
at the J and K inputs may be changed without  
affecting the levels at the outputs. These versatile  
flip-flops can perform as toggle flip-flops by  
grounding K and trying J high. They also can  
perform as D-type flip-flops if J and K are tied  
together.  
1CLK  
1PRE  
1Q  
2K  
2CLK  
11 2PRE  
10  
9
1Q  
2Q  
2Q  
GND  
SN54F109 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
1K  
1CLK  
NC  
4
5
6
7
8
2J  
17  
16  
15  
14  
2K  
NC  
1PRE  
1Q  
2CLK  
2PRE  
9 10 11 12 13  
The SN54F109 is characterized for operation over  
the full military temperature range of 55°C to  
125°C. The SN74F109 is characterized for  
operation from 0°C to 70°C.  
NC – No internal connection  
FUNCTION TABLE  
INPUTS  
OUTPUTS  
PRE  
L
CLR  
H
CLK  
X
J
X
X
X
L
K
X
X
X
L
Q
H
L
Q
L
H
L
X
H
H
H
L
L
X
H
H
L
H
H
H
H
L
L
Toggle  
H
H
H
H
X
Q
Q
0
0
H
H
H
X
H
L
H
H
L
Q
Q
0
0
The output levels are not guaranteed to meet the minimum  
levelsforV .Furthermore,thisconfigurationisnonstable;  
OH  
that is, it will not persist when PRE or CLR returns to its  
inactive (high) level.  
Copyright 1993, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
2–1  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

5962-9758001QEA 替代型号

型号 品牌 替代类型 描述 数据表
SNJ54F109J TI

完全替代

DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

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