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5962-9461108HXC PDF预览

5962-9461108HXC

更新时间: 2024-11-01 20:15:47
品牌 Logo 应用领域
WEDC 静态存储器
页数 文件大小 规格书
40页 287K
描述
Cache SRAM Module, 512KX32, 25ns, CMOS, CPGA66, HEX-IN-LINE, SINGLE CAVITY, WITH STANDOFFS-66

5962-9461108HXC 数据手册

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REVISIONS  
LTR  
F
DESCRIPTION  
DATE (YR-MO-DA)  
99-04-22  
APPROVED  
Figure 1; changed case outline M to be available in either a single or  
dual cavity package. Added vendor CAGE code 0EU86 for device  
types 05 through 10. -sld  
K. A. Cottongim  
G
H
Added device types 11 through 16.  
99-08-18  
00-04-06  
Raymond Monnin  
Raymond Monnin  
Add note to paragraph 1.2.2 and table I, conditions. Add thermal  
resistance, junction-to-case (θJC) for all case outlines. Add case  
outline 9.  
J
Table I, ICC change maximum limits and ISB change maximum limits.  
Figure 1, case outline M, correct diagram adding "c" dimension, lead  
thickness and change dimension A2 maximum from 0.020" to 0.025".  
00-06-19  
Raymond Monnin  
K
L
Figure 1, case outline 9, minimum dimension for D2/E2, change  
0.990 inches to 0.980 inches and 25.15 mm to 24.89 mm.  
01-5-16  
Raymond Monnin  
Raymond Monnin  
Table I; Operating supply current (ICC) changed the maximum limit for  
device types 9 and 15 at f = 50 MHz from 700 mA to 725 mA and for  
device types 10 and 16 at f = 58.8 MHz from 700 mA to 750 mA. -sld  
01-12-21  
M
N
P
Added device types 17 through 20. -sld  
Added case outline A. -sld  
02-11-18  
03-02-24  
03-12-19  
04-05-03  
Raymond Monnin  
Raymond Monnin  
Raymond Monnin  
Raymond Monnin  
Added case outline B. Added note to paragraph 1.2.4. -sld  
R
Table I; Changed the IOL from 8 mA to 6 mA for device types 07-10  
and 13 -20 for the VOL test. Editorial changes throughout. -sld  
REV  
SHEET  
REV  
R
R
R
R
R
R
R
21  
R
R
22  
R
R
23  
R
R
24  
R
R
25  
R
R
26  
R
R
27  
R
R
28  
R
R
29  
R
R
30  
R
R
SHEET  
15  
16  
17  
18  
19  
20  
31  
R
REV STATUS  
OF SHEETS  
REV  
R
R
R
SHEET  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
PMIC N/A  
PREPARED BY  
Gary Zahn  
DEFENSE SUPPLY CENTER COLUMBUS  
STANDARD  
MICROCIRCUIT  
DRAWING  
CHECKED BY  
Michael C. Jones  
COLUMBUS, OHIO 43216  
http://www.dscc.dla.mil  
THIS DRAWING IS  
AVAILABLE  
FOR USE BY ALL  
DEPARTMENTS  
APPROVED BY  
Kendall A. Cottongim  
MICROCIRCUIT, HYBRID, MEMORY,  
DIGITAL, 512K x 32-BIT, STATIC RANDOM  
ACCESS MEMORY, CMOS  
AND AGENCIES OF THE  
DEPARTMENT OF DEFENSE  
DRAWING APPROVAL DATE  
95-11-13  
AMSC N/A  
REVISION LEVEL  
SIZE  
A
CAGE CODE  
67268  
R
5962-94611  
SHEET  
1 OF 31  
DSCC FORM 2233  
APR 97  
5962-E251-04  

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