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5962-9232404MXC PDF预览

5962-9232404MXC

更新时间: 2024-11-03 05:52:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
12页 280K
描述
Non-Volatile SRAM, 8KX8, 55ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

5962-9232404MXC 数据手册

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STK11C68  
STK11C68-M SMD#5962-92324  
8K x 8 nvSRAM  
QuantumTrap™ CMOS  
Nonvolatile Static RAM  
FEATURES  
DESCRIPTION  
• 25ns, 35ns, 45ns and 55ns Access Times  
The Simtek STK11C68 is a fast static RAM with a  
nonvolatile element incorporated in each static  
memory cell. The SRAM can be read and written an  
unlimited number of times, while independent non-  
volatile data resides in the Nonvolatile Elements.  
Data transfers from the SRAM to the Nonvolatile Ele-  
ments (the STORE operation), or from Nonvolatile  
Elements to SRAM (the RECALL operation), take  
place using a software sequence. Transfers from the  
Nonvolatile Elements to the SRAM (the RECALL  
operation) also take place automatically on restora-  
tion of power.  
STORE to Nonvolatile Elements Initiated by  
Software  
RECALL to SRAM Initiated by Software or  
Power Restore  
• 10mA Typical ICC at 200ns Cycle Time  
• Unlimited READ, WRITE and RECALL Cycles  
• 1,000,000 STORE Cycles to Nonvolatile Ele-  
ments (Industrial/Commercial)  
• 100-Year Data Retention (Industrial/Commer-  
cial)  
• Commercial, Industrial and Military Tempera-  
tures  
The STK11C68 is pin-compatible with industry-  
standard SRAMs. MIL-STD-883 device is also  
available (STK11C68-M).  
• 28-Pin DIP, SOIC and LCC Packages  
BLOCK DIAGRAM  
PIN CONFIGURATIONS  
1
NC  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
VCC  
W
NC  
A8  
A9  
A11  
G
A10  
E
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
QUANTUM TRAP  
128 x 512  
2
3
4
A5  
5
STORE  
6
A6  
STORE/  
RECALL  
CONTROL  
7
A7  
8
STATIC RAM  
ARRAY  
9
RECALL  
A8  
10  
11  
12  
13  
14  
A0  
128 x 512  
DQ0  
DQ1  
DQ2  
VSS  
A9  
A11  
A12  
SOFTWARE  
DETECT  
A0 - A12  
28 - LCC  
28 - DIP  
28 - SOIC  
DQ0  
DQ1  
DQ2  
COLUMN I/O  
PIN NAMES  
COLUMN DEC  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
A
- A  
12  
Address Inputs  
Write Enable  
Data In/Out  
Chip Enable  
Output Enable  
Power (+ 5V)  
Ground  
0
W
A0 A1 A2 A3 A4 A10  
G
DQ - DQ  
0
7
E
E
G
W
V
CC  
SS  
V
March 2006  
1
Document Control # ML0007 rev 0.2  

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