Datasheet > 5962-9232404MXC

5962-9232404MXC

更新时间： 2023-01-03 04:14:18

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
12页	280K
描述
Non-Volatile SRAM, 8KX8, 55ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

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数据手册

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5962-9232404MXC 数据手册

STK11C68

SRAM WRITE CYCLES #1 & #2

(V = 5.0V + 10%)

SYMBOLS

STK11C68-25

STK11C68-35

STK11C68-45

STK11C68-55

NO.

PARAMETER

UNITS

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

Write Cycle Time

AVAV

Write Pulse Width

WLWH

WLEH

Chip Enable to End of Write

Data Set-up to End of Write

Data Hold after End of Write

Address Set-up to End of Write

Address Set-up to Start of Write

Address Hold after End of Write

Write Enable to Output Disable

Output Active after End of Write

ELWH

DVWH

WHDX

ELEH

DVEH

EHDX

AVWH

AVEH

AVWL

AVEL

WHAX

h, i

EHAX

WLQZ

WHQX

Note i: If W is low when E goes low, the outputs remain in the high-impedance state.

Note j: E or W must be ≥ V_IHduring address transitions.

SRAM WRITE CYCLE #1: W Controlled

AVAV

ADDRESS

WHAX

ELWH

AVWH

AVWL

WLWH

DVWH

WHDX

DATA IN

DATA VALID

WLQZ

WHQX

HIGH IMPEDANCE

DATA OUT

PREVIOUS DATA

SRAM WRITE CYCLE #2: E Controlled

AVAV

ADDRESS

ELEH

AVEL

EHAX

AVEH

WLEH

DVEH

EHDX

DATA IN

DATA VALID

HIGH IMPEDANCE

DATA OUT

March 2006

Document Control # ML0007 rev 0.2

1 2 345 6 7...12

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