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5962-8601506YA PDF预览

5962-8601506YA

更新时间: 2024-11-04 15:43:55
品牌 Logo 应用领域
艾迪悌 - IDT 静态存储器内存集成电路
页数 文件大小 规格书
8页 86K
描述
CDIP-22, Tube

5962-8601506YA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:CDIP
包装说明:DIP, DIP22,.3针数:22
Reach Compliance Code:not_compliantECCN代码:3A001.A.2.C
HTS代码:8542.32.00.41风险等级:5.26
最长访问时间:55 nsI/O 类型:SEPARATE
JESD-30 代码:R-GDIP-T22JESD-609代码:e0
长度:27.051 mm内存密度:65536 bit
内存集成电路类型:STANDARD SRAM内存宽度:1
湿度敏感等级:1功能数量:1
端口数量:1端子数量:22
字数:65536 words字数代码:64000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-55 °C组织:64KX1
输出特性:3-STATE可输出:NO
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP22,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:5.08 mm最大待机电流:0.001 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.09 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:TIN LEAD
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

5962-8601506YA 数据手册

 浏览型号5962-8601506YA的Datasheet PDF文件第2页浏览型号5962-8601506YA的Datasheet PDF文件第3页浏览型号5962-8601506YA的Datasheet PDF文件第4页浏览型号5962-8601506YA的Datasheet PDF文件第5页浏览型号5962-8601506YA的Datasheet PDF文件第6页浏览型号5962-8601506YA的Datasheet PDF文件第7页 
IDT7187S  
IDT7187L  
CMOS Static RAM  
64K (64K x 1-Bit)  
Description  
Features  
TheIDT7187isa65,536-bithigh-speedstaticRAMorganizedas64K  
x1.ItisfabricatedusingIDT’shigh-performance,high-reliabilityCMOS  
technology.Accesstimesasfastas25nsareavailable.  
Both the standard (S) and low-power (L) versions of the IDT7187  
provide two standby modesISB and ISB1. ISB provides low-power  
operation;ISB1 provides ultra-low-poweroperation. The low-power(L)  
version also provides the capability for data retention using battery  
backup. When using a 2V battery, the circuit typically consumes only  
30µW.  
Ease of system design is achieved by the IDT7187 with full  
asynchronous operation,alongwithmatchingaccess andcycletimes.  
Thedeviceispackagedinanindustrystandard22-pin,300milceramic  
DIP.  
High speed (equal access and cycle time)  
Military: 25/35/45/55/70/85ns (max.)  
Low power consumption  
Battery backup operation2V data retention  
(L version only)  
JEDEC standard high-density 22-pin ceramic  
DIP packaging  
Produced with advanced CMOS high-performance  
technology  
Separate data input and output  
Input and output directly TTL-compatible  
Military product compliant to MIL-STD-883, Class B  
Militarygradeproductismanufacturedincompliancewiththelatest  
revision of MIL-STD-883, Class B, making it ideally suited to military  
temperature applications demandingthe highestlevelofperformance  
and reliability.  
Functional Block Diagram  
A
A
A
CC  
V
GND  
65,536-BIT  
MEMORY ARRAY  
ROW  
SELECT  
A
A
A
A
CS  
DATAOUT  
IN  
DATA  
COLUMN I/O  
WE  
2986 drw 01  
A
A
A
A
A
A
A
AUGUST 2000  
1
©2000IntegratedDeviceTechnology,Inc.  
DSC-2986/08  

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