54ACT283L

更新时间： 2024-09-17 22:56:11

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
8页	188K
描述
4-Bit Binary Full Adder with Fast Carry

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中文翻译

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54ACT283L 数据手册

September 1998

54ACT283

4-Bit Binary Full Adder with Fast Carry

General Description

Features

n Guaranteed 4000V minimum ESD protection

n Outputs source/sink 24 mA

n TTL-compatible inputs

The ’ACT283 high-speed 4-bit binary full adder with internal

carry lookahead accepts two 4-bit binary words (A₀–A₃,

B₀–B₃) and a Carry input (C₀). It generates the binary Sum

outputs (S₀–S₃) and the Carry output (C₄) from the most sig-

nificant bit. The ’ACT283 will operate with either active HIGH

or active LOW operands (positive or negative logic).

n Available to Mil-Std-883

Logic Symbols

Pin Assignment for LCC

DS100977-1

IEEE/IEC

DS100977-3

Functional Description

The ’ACT283 adds two 4-bit binary words (A plus B) plus the

incoming Carry (C₀). The binary sum appears on the Sum

(S₀–S₃) and outgoing carry (C₄) outputs. The binary weight

of the various inputs and outputs is indicated by the subscript

numbers, representing powers of two.

2⁰(A₀+ B₀+ C₀) + 2¹(A₁+ B₁)

+ 2²(A₂+ B₂) + 2³(A₃+ B₃)

S₀+ 2S₁+ 4S₂+ 8S₃+ 16C₄

Where (+) plus

DS100977-4

Interchanging inputs of equal weight does not affect the op-

eration. Thus C₀, A₀, B₀can be arbitrarily assigned to pins 5,

6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages.

Due to the symmetry of the binary add function, the ’ACT283

can be used either with all inputs and outputs active HIGH

(positive logic) or with all inputs and outputs active LOW

(negative logic). See Figure 1. Note that if C₀is not used it

must be tied LOW for active HIGH logic or tied HIGH for ac-

tive LOW logic.

Connection Diagrams

Pin Assignment

for DIP and Flatpak

Due to pin limitations, the intermediate carries of the

’ACT283 are not brought out for use as inputs or outputs.

However, other means can be used to effectively insert a

carry into, or bring a carry out from, an intermediate stage.

Figure 2 shows how to make a 3-bit adder. Tying the oper-

and inputs of the fourth adder (A₃, B₃) LOW makes S₃de-

pendent only on, and equal to, the carry from the third adder.

Using somewhat the same principle, Figure 3 shows a way

of dividing the ’ACT283 into a 2-bit and a 1-bit adder. The

third stage adder (A₂, B₂, S₂) is used merely as a means of

getting a carry (C₁₀) signal into the fourth stage (via A₂and

B₂) and bringing out the carry from the second stage on S₂.

DS100977-2

DS100977

www.national.com

12 3 4 5 6 7 8

中文翻译

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与54ACT283L相关器件

型号	品牌	获取价格	描述	数据表
54ACT283LM	TI	获取价格	ACT SERIES, 4-BIT ADDER/SUBTRACTOR, CQCC20, CERAMIC, LCC-20
54ACT283LMQB	ETC	获取价格	Binary Adder
54ACT299	NSC	获取价格	8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
54ACT299DM	NSC	获取价格	IC ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, C
54ACT299DM	TI	获取价格	ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP
54ACT299DM	FAIRCHILD	获取价格	Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, CDIP20, CER
54ACT299DMQB	FAIRCHILD	获取价格	Parallel In Parallel Out, ACT Series, 8-Bit, Bidirectional, True Output, CMOS, CDIP20, CER
54ACT299DMQB	NSC	获取价格	暂无描述
54ACT299FM	TI	获取价格	ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP
54ACT299FM-MLS	TI	获取价格	ACT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP

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