2SJ244

更新时间： 2024-02-14 07:13:39

品牌	Logo	应用领域
日立 - HITACHI		/
页数	文件大小	规格书
8页	47K
描述
Silicon P-Channel MOS FET

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技术参数
数据手册

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2SJ244 技术参数

生命周期：	Transferred	零件包装代码：	SC-62
包装说明：	SMALL OUTLINE, R-PSSO-F3	针数：	3
Reach Compliance Code：	unknown	风险等级：	5.27
最大漏源导通电阻：	0.9 Ω	JESD-30 代码：	R-PSSO-F3
端子数量：	3	封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
认证状态：	Not Qualified	表面贴装：	YES
端子形式：	FLAT	端子位置：	SINGLE
Base Number Matches：	1

2SJ244 数据手册

2SJ244

Absolute Maximum Ratings (Ta = 25°C)

Item

Symbol

V_DSS

Ratings

Unit

Drain to source voltage

Gate to source voltage

Drain current

–12

V_GSS

±7

I_D

±2

Drain peak current

I_D(pulse)

Pch*²

Tch

±4

Channel dissipation

Channel temperature

Storage temperature

Notes: 1. PW ≤ 100 µs, duty cycle ≤ 10%

°C

150

Tstg

–55 to +150

2. Value on the alumina ceramic board (12.5×20×0.7 mm)

3. Marking is “JY”.

Electrical Characteristics (Ta = 25°C)

Item

Symbol Min

Typ

Max

Unit

Test conditions

Drain to source breakdown

voltage

V_(BR)DSS–12

—

I_D= –1 mA, V_GS= 0

Gate to source breakdown

voltage

V_(BR)GSS±7

—

I_G= ±10 µA, V_DS= 0

Gate to source cutoff current

I_GSS

—

±5

µA

V_GS= ±6 V, V_DS= 0

Zero gate voltage drain current I_DSS

—

–1

V_DS= –8 V, V_GS= 0

Gate to source cutoff voltage

V_GS(off)

–0.4

—

–1.4

0.9

I_D= –100 µA, V_DS= –5 V

I_D= –0.5 A*¹, V_GS= –2.5 V

Static drain to source on state R_DS(on)1

resistance

0.65

Ω

Static drain to source on state R_DS(on)2

resistance

—

0.5

—

Ω

I_D= –1 A*¹, V_GS= –4 V

Forward transfer admittance

Input capacitance

|y_fs|

—

1.8

—

I_D= –1 A*¹, V_DS= –5 V

V_DS= –5 V, V_GS= 0,

f = 1 MHz

Ciss

Coss

Crss

t_(on)

130

Output capacitance

Reverse transfer capacitance

Turn-on delay time

260

365

1450

—

I_D= –0.2 A*¹, Vin = –4 V,

R_L= 51 Ω

I_F= 4 A*¹, V_GS= 0

Turn-off delay time

t_(off)

Body to drain diode forward

voltage

V_DF

Note: 1. Pulse test

123 4 5 6 7 8

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