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2N5912-E3 PDF预览

2N5912-E3

更新时间: 2024-11-25 14:48:55
品牌 Logo 应用领域
威世 - VISHAY /
页数 文件大小 规格书
7页 77K
描述
Small Signal Field-Effect Transistor, N-Channel, Junction FET

2N5912-E3 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:,Reach Compliance Code:unknown
风险等级:5.46FET 技术:JUNCTION
JESD-609代码:e3湿度敏感等级:1
最高工作温度:150 °C极性/信道类型:N-CHANNEL
最大功率耗散 (Abs):0.5 W子类别:FET General Purpose Small Signal
表面贴装:NO端子面层:Matte Tin (Sn)
Base Number Matches:1

2N5912-E3 数据手册

 浏览型号2N5912-E3的Datasheet PDF文件第2页浏览型号2N5912-E3的Datasheet PDF文件第3页浏览型号2N5912-E3的Datasheet PDF文件第4页浏览型号2N5912-E3的Datasheet PDF文件第5页浏览型号2N5912-E3的Datasheet PDF文件第6页浏览型号2N5912-E3的Datasheet PDF文件第7页 
2N5911/5912  
Vishay Siliconix  
Matched N-Channel JFET Pairs  
PRODUCT SUMMARY  
Part Number VGS(off) (V) V(BR)GSS Min (V) gfs Min (mS) IG Typ (pA) jVGS1 – VGS2j Max (mV)  
2N5911  
2N5912  
–1 to –5  
–1 to –5  
–25  
–25  
5
5
–1  
–1  
10  
15  
FEATURES  
BENEFITS  
APPLICATIONS  
D Two-Chip Design  
D High Slew Rate  
D Minimum Parasitics Ensuring Maximum  
D Wideband Differential Amps  
High-Frequency Performance  
D High-Speed, Temp-Compensated,  
D Improved Op Amp Speed, Settling Time Accuracy  
D Minimum Input Error/Trimming Requirement  
D Insignificant Signal Loss/Error Voltage  
D High System Sensitivity  
Single-Ended Input Amps  
D Low Offset/Drift Voltage  
D Low Gate Leakage: 1 pA  
D Low Noise  
D High Speed Comparators  
D Impedance Converters  
D High CMRR: 85 dB  
D Minimum Error with Large Input Signal  
DESCRIPTION  
The 2N5911/5912 are matched pairs of JFETs mounted in a  
TO-78 package. This two-chip design reduces parasitics and  
gives better performance at high frequencies while ensuring  
extremely tight matching.  
For similar products see the SO-8 packaged  
SST440/SST441, the TO-71 packaged U440/U441, the  
low-noise SST/U401 series, and the low-leakage U421/423  
data sheets.  
The hermetically-sealed TO-78 package is available with full  
military screening per MIL-S-19500 (see Military Information).  
TO-78  
S
G
2
1
1
3
7
D
1
D
2
2
6
5
G
1
S
2
4
Case  
Top View  
ABSOLUTE MAXIMUM RATINGS  
a
Gate-Drain, Gate-Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V  
Gate-Gate Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "80 V  
Gate Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Power Dissipation :  
Notes  
Per Side . . . . . . . . . . . . . . . . . . . . . . . . 367 mW  
b
Total . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW  
1
Lead Temperature ( / ” from case for 10 sec.) . . . . . . . . . . . . . . . . . . . 300_C  
16  
a. Derate 3 mW/_C above 25_C  
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 200_C  
b. Derate 4 mW/_C above 25_C  
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 150_C  
For applications information see AN102.  
Document Number: 70255  
S-04031—Rev. D, 04-Jun-01  
www.vishay.com  
8-1  

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