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24C65-E/P

更新时间： 2024-02-04 06:13:43

品牌	Logo	应用领域
美国微芯 - MICROCHIP		存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
24页	285K
描述
64K 1.8V I2C Smart Serial O EEPROM

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24C65-E/P 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.19
最大时钟频率 (fCLK)：	0.4 MHz	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	5.245 mm
内存密度：	65536 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	8192 words
字数代码：	8000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	8KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	2.03 mm	串行总线类型：	I2C
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	5.23 mm
最长写入周期时间 (tWC)：	5 ms	Base Number Matches：	1

24C65-E/P 数据手册

24AA65/24LC65/24C65

3.6

Device Addressing

4.0

4.1

WRITE OPERATION

Byte Write

A control byte is the first byte received following the

Start condition from the master device. The control byte

consists of a four-bit control code, for the 24XX65 this

is set as ‘1010’ binary for read and write operations.

The next three bits of the control byte are the device

select bits (A2, A1, A0). They are used by the master

device to select which of the eight devices are to be

accessed. These bits are in effect the three Most

Significant bits of the word address. The last bit of the

control byte defines the operation to be performed.

When set to a one a read operation is selected, when

set to a zero a write operation is selected. The next two

bytes received define the address of the first data byte

(Figure 4-1). Because only A12..A0 are used, the

upper three address bits must be zeros. The Most

Significant bit of the Most Significant Byte is transferred

first. Following the Start condition, the 24XX65

monitors the SDA bus checking the device type

identifier being transmitted. Upon receiving a ‘1010’

code and appropriate device select bits, the slave

device (24XX65) outputs an Acknowledge signal on the

SDA line. Depending upon the state of the R/W bit, the

24XX65 will select a read or write operation.

Following the Start condition from the master, the con-

trol code (four bits), the device select (three bits), and

the R/W bit which is a logic low, is placed onto the bus

by the master transmitter. This indicates to the

addressed slave receiver (24XX65) that a byte with a

word address will follow after it has generated an

Acknowledge bit during the ninth clock cycle. There-

fore, the next byte transmitted by the master is the

high-order byte of the word address and will be written

into the address pointer of the 24XX65. The next byte

is the Least Significant Address Byte. After receiving

another Acknowledge signal from the 24XX65, the

master device will transmit the data word to be written

into the addressed memory location. The 24XX65

acknowledges again and the master generates a Stop

condition. This initiates the internal write cycle, and

during this time the 24XX65 will not generate

Acknowledge signals (Figure 4-1).

4.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24XX65 in the same way as

in a byte write. But instead of generating a Stop

condition, the master transmits up to eight pages of

eight data bytes each (64 bytes total), which are

temporarily stored in the on-chip page cache of the

24XX65. They will be written from the cache into the

EEPROM array after the master has transmitted a Stop

condition. After the receipt of each word, the six lower

order address pointer bits are internally incremented by

one. The higher order seven bits of the word address

remain constant. If the master should transmit more

than eight bytes prior to generating the Stop condition

(writing across a page boundary), the address counter

(lower three bits) will roll over and the pointer will be

incremented to point to the next line in the cache. This

can continue to occur up to eight times or until the cache

is full, at which time a Stop condition should be

generated by the master. If a Stop condition is not

received, the cache pointer will roll over to the first line

(byte 0) of the cache, and any further data received will

overwrite previously captured data. The Stop condition

can be sent at any time during the transfer. As with the

byte write operation, once the Stop condition is received

an internal write cycle will begin. The 64-byte cache will

continue to capture data until a Stop condition occurs or

the operation is aborted (Figure 4-2).

Operation Control Code Device Select R/W

Read

Write

1010

Device Address

DeviceAddress

FIGURE 3-2:

CONTROL BYTE

ALLOCATION

START

READ/WRITE

SLAVE ADDRESS

R/W

DS21073J-page 6

 2003 Microchip Technology Inc.

1...3 4 567 8 9...24

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与24C65-E/P相关器件

型号	品牌	描述	获取价格	数据表
24C65-E/PG	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8	获取价格
24C65-E/SM	MICROCHIP	64K 1.8V I2C Smart Serial O EEPROM	获取价格
24C65-E/SMG	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8	获取价格
24C65-EP	MICROCHIP	64K 5.0V I 2 C Smart Serial EEPROM	获取价格
24C65-ESM	MICROCHIP	64K 5.0V I 2 C Smart Serial EEPROM	获取价格
24C65I/P	MICROCHIP	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8	获取价格

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