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24C65-E/P

更新时间： 2024-01-15 17:42:16

品牌	Logo	应用领域
美国微芯 - MICROCHIP		存储内存集成电路光电二极管双倍数据速率可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
页数	文件大小	规格书
24页	285K
描述
64K 1.8V I2C Smart Serial O EEPROM

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技术参数
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替代型号

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24C65-E/P 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	SOIC
包装说明：	5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8	针数：	8
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.19
最大时钟频率 (fCLK)：	0.4 MHz	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	5.245 mm
内存密度：	65536 bit	内存集成电路类型：	EEPROM
内存宽度：	8	功能数量：	1
端子数量：	8	字数：	8192 words
字数代码：	8000	工作模式：	SYNCHRONOUS
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	8KX8	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	并行/串行：	SERIAL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	2.03 mm	串行总线类型：	I2C
最大供电电压 (Vsup)：	6 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	40	宽度：	5.23 mm
最长写入周期时间 (tWC)：	5 ms	Base Number Matches：	1

24C65-E/P 数据手册

24AA65/24LC65/24C65

5.4

Contiguous Addressing Across

Multiple Devices

5.0

READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types

of read operations: current address read, random read

and sequential read.

The device select bits A2, A1, A0 can be used to

expand the contiguous address space for up to 512K

bits by adding up to eight 24XX65's on the same bus.

In this case, software can use A0 of the control byte as

address bit A13, A1 as address bit A14 and A2 as

address bit A15.

5.1

Current Address Read

The 24XX65 contains an address counter that main-

tains the address of the last word accessed, internally

incremented by one. Therefore, if the previous access

(either a read or write operation) was to address n (n is

any legal address), the next current address read

operation would access data from address n + 1. Upon

receipt of the slave address with R/W bit set to one, the

24XX65 issues an acknowledge and transmits the

eight-bit data word. The master will not acknowledge

the transfer but does generate a Stop condition and the

24XX65 discontinues transmission (Figure 4-3).

5.5

Noise Protection

The SCL and SDA inputs have filter circuits which

suppress noise spikes to assure proper device

operation even on a noisy bus. All I/O lines incorporate

Schmitt Triggers for 400 kHz (Fast mode) compatibility.

5.6

High Endurance Block

The location of the high endurance block within the

memory map is programmed by setting the leading bit

7 (S/HE) of the configuration byte to ‘0’. The upper bits

of the address loaded in this command will determine

which 4K block within the memory map will be set to

high endurance. This block will be capable of

10,000,000 erase/write cycles typical (Figure 8-1).

5.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the word address must

be set. This is done by sending the word address to the

24XX65 as part of a write operation (R/W bit set to ‘0’).

After the word address is sent, the master generates a

Start condition following the acknowledge. This

terminates the write operation, but not before the

internal address pointer is set. Then the master issues

the control byte again, but with the R/W bit set to a one.

The 24XX65 will then issue an acknowledge and

transmit the eight-bit data word. The master will not

acknowledge the transfer, but does generate a Stop

condition which causes the 24XX65 to discontinue

transmission (Figure 4-4).

The high endurance block will retain its value as the

high endurance block even if it resides within the

security block range. The high endurance setting

always takes precedence to the security setting.

Note:

The high endurance block cannot be

changed after the security option has been

set with a length greater than zero. If the

H.E. block is not programmed by the user,

the default location is the highest block of

memory which starts at location 0x1E00

and ends at 0x1FFF.

5.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 24XX65 transmits the

first data byte, the master issues an acknowledge as

opposed to the Stop condition used in a random read.

This acknowledge directs the 24XX65 to transmit the

next sequentially addressed 8-bit word (Figure 4-5).

Following the final byte transmitted to the master, the

master will NOT generate an acknowledge, but will

generate a Stop condition.

To provide sequential reads the 24XX65 contains an

internal address pointer which is incremented by one at

the completion of each operation. This address pointer

allows the entire memory contents to be serially read

during one operation.

 2003 Microchip Technology Inc.

DS21073J-page 9

1...6 7 8910 11 12...24

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24C65-E/P 替代型号

型号	品牌	替代类型	描述	数据表
24C65/P	MICROCHIP	功能相似	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, PLASTIC, MS-001, DIP-8
24C65I/P	MICROCHIP	功能相似	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8
24C65-I/P	MICROCHIP	功能相似	64K 1.8V I2C Smart Serial O EEPROM

与24C65-E/P相关器件

型号	品牌	获取价格	描述	数据表
24C65-E/PG	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8
24C65-E/SM	MICROCHIP	获取价格	64K 1.8V I2C Smart Serial O EEPROM
24C65-E/SMG	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8
24C65-EP	MICROCHIP	获取价格	64K 5.0V I 2 C Smart Serial EEPROM
24C65-ESM	MICROCHIP	获取价格	64K 5.0V I 2 C Smart Serial EEPROM
24C65I/P	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8
24C65-I/P	MICROCHIP	获取价格	64K 1.8V I2C Smart Serial O EEPROM
24C65-I/PG	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8
24C65I/SM	MICROCHIP	获取价格	8K X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 5.28 MM, ROHS COMPLIANT, PLASTIC, SOIJ-8
24C65-I/SM	MICROCHIP	获取价格	64K 1.8V I2C Smart Serial O EEPROM

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