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24C02ATE/SM

更新时间： 2024-01-25 06:05:24
品牌 Logo 应用领域
美国微芯 - MICROCHIP /
页数 文件大小 规格书
12页 86K
描述
256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.207 INCH, PLASTIC, SOIC-8

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中文翻译

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24C02ATE/SM 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Not Recommended零件包装代码：WAFER
包装说明：DIE, WAFER针数：5
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.38
其他特性：2-WIRE SERIAL INTERFACE; DATA RETENTION > 200 YEARS; 1000000 ERASE/WRITE CYCLES GUARANTEED最大时钟频率 (fCLK)：0.4 MHz
数据保留时间-最小值：200耐久性：1000000 Write/Erase Cycles
I2C控制字节：1010XXXRJESD-30 代码：R-XUUC-N5
JESD-609代码：e3内存密度：2048 bit
内存集成电路类型：EEPROM内存宽度：8
功能数量：1端子数量：5
字数：256 words字数代码：256
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：256X8
输出特性：OPEN-DRAIN封装主体材料：UNSPECIFIED
封装代码：DIE封装等效代码：WAFER
封装形状：RECTANGULAR封装形式：UNCASED CHIP
并行/串行：SERIAL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
串行总线类型：I2C最大待机电流：0.0001 A
子类别：EEPROMs最大压摆率：0.003 mA
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：NO LEAD
端子位置：UPPER处于峰值回流温度下的最长时间：NOT SPECIFIED
最长写入周期时间 (tWC)：10 msBase Number Matches：1

24C02ATE/SM 数据手册

 浏览型号24C02ATE/SM的Datasheet PDF文件第2页浏览型号24C02ATE/SM的Datasheet PDF文件第3页浏览型号24C02ATE/SM的Datasheet PDF文件第4页浏览型号24C02ATE/SM的Datasheet PDF文件第6页浏览型号24C02ATE/SM的Datasheet PDF文件第7页浏览型号24C02ATE/SM的Datasheet PDF文件第8页 
24C01SC/02SC  
4.0  
BUS CHARACTERISTICS  
5.0  
WRITE OPERATION  
4.1  
Slave Address  
5.1  
Byte Write  
After generating a START condition, the bus master  
transmits the slave address consisting of a 4-bit device  
code (1010) for the 24C01SC/02SC, followed by three  
don't care bits.  
Following the start signal from the master, the device  
code (4 bits), the don't care bits (3 bits), and the R/W  
bit, which is a logic low, is placed onto the bus by the  
master transmitter. This indicates to the addressed  
slave receiver that a byte with a word address will follow  
after it has generated an acknowledge bit during the  
ninth clock cycle. Therefore, the next byte transmitted  
by the master is the word address and will be written  
into the address pointer of the 24C01SC/02SC. After  
receiving another acknowledge signal from the  
24C01SC/02SC, the master device will transmit the  
data word to be written into the addressed memory  
location.The 24C01SC/02SC acknowledges again and  
the master generates a stop condition.This initiates the  
internal write cycle, and during this time the  
24C01SC/02SC will not generate acknowledge signals  
(Figure 5-1).  
The eighth bit of slave address determines if the master  
device wants to read or write to the 24C01SC/02SC  
(Figure 4-1).  
The 24C01SC/02SC monitors the bus for its corre-  
sponding slave address all the time. It generates an  
acknowledge bit if the slave address was true, and it is  
not in a programming mode.  
Control  
Code  
Chip  
Select  
Operation  
R/W  
Read  
Write  
1010  
1010  
XXX  
XXX  
1
0
5.2  
Page Write  
FIGURE 4-1: CONTROL BYTE  
ALLOCATION  
The write control byte, word address, and the first data  
byte are transmitted to the 24C01SC/02SC in the same  
way as in a byte write. But instead of generating a stop  
condition, the master transmits up to eight data bytes to  
the 24C01SC/02SC, which are temporarily stored in  
the on-chip page buffer and will be written into the  
memory after the master has transmitted a stop condi-  
tion. After the receipt of each word, the three lower  
order address pointer bits are internally incremented by  
one. The higher order five bits of the word address  
remains constant. If the master should transmit more  
than eight words prior to generating the stop condition,  
the address counter will roll over and the previously  
received data will be overwritten. As with the byte write  
operation, once the stop condition is received an inter-  
nal write cycle will begin (Figure 5-2).  
START  
READ/WRITE  
R/W  
X
A
SLAVE ADDRESS  
1
0
1
0
X
X
X = Don’t care  
FIGURE 5-1: BYTE WRITE  
S
BUS ACTIVITY  
MASTER  
T
A
R
T
S
T
O
P
CONTROL  
BYTE  
WORD  
ADDRESS  
DATA  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY  
FIGURE 5-2: PAGE WRITE  
S
BUS ACTIVITY  
MASTER  
T
S
T
O
P
CONTROL  
BYTE  
WORD  
ADDRESS (n)  
A
R
T
DATA n  
DATAn + 1  
DATAn + 7  
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY  
1996 Microchip Technology Inc.  
Preliminary  
DS21170A-page 5  
12345678...12

中文翻译

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