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24C02ATE/SM

更新时间： 2024-01-22 00:56:10

品牌	Logo	应用领域
美国微芯 - MICROCHIP		/
页数	文件大小	规格书
12页	86K
描述
256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.207 INCH, PLASTIC, SOIC-8

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技术参数
数据手册

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24C02ATE/SM 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Not Recommended	零件包装代码：	WAFER
包装说明：	DIE, WAFER	针数：	5
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.51	风险等级：	5.38
其他特性：	2-WIRE SERIAL INTERFACE; DATA RETENTION > 200 YEARS; 1000000 ERASE/WRITE CYCLES GUARANTEED	最大时钟频率 (fCLK)：	0.4 MHz
数据保留时间-最小值：	200	耐久性：	1000000 Write/Erase Cycles
I2C控制字节：	1010XXXR	JESD-30 代码：	R-XUUC-N5
JESD-609代码：	e3	内存密度：	2048 bit
内存集成电路类型：	EEPROM	内存宽度：	8
功能数量：	1	端子数量：	5
字数：	256 words	字数代码：	256
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	256X8
输出特性：	OPEN-DRAIN	封装主体材料：	UNSPECIFIED
封装代码：	DIE	封装等效代码：	WAFER
封装形状：	RECTANGULAR	封装形式：	UNCASED CHIP
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
串行总线类型：	I2C	最大待机电流：	0.0001 A
子类别：	EEPROMs	最大压摆率：	0.003 mA
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	NO LEAD
端子位置：	UPPER	处于峰值回流温度下的最长时间：	NOT SPECIFIED
最长写入周期时间 (tWC)：	10 ms	Base Number Matches：	1

24C02ATE/SM 数据手册

24C01SC/02SC

3.4

Data Valid (D)

2.0

FUNCTIONAL DESCRIPTION

The 24C01SC/02SC supports a bi-directional two-wire

bus and data transmission protocol. A device that

sends data onto the bus is deﬁned as transmitter, and

a device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions, while the

24C01SC/02SC works as slave. Both master and slave

can operate as transmitter or receiver, but the master

device determines which mode is activated.

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited, although only the last 16

will be stored when doing a write operation. When an

overwrite does occur, it will replace data in a ﬁrst in ﬁrst

out fashion.

3.0

BUS CHARACTERISTICS

The following bus protocol has been deﬁned:

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

3.5

Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

Accordingly, the following bus conditions have been

deﬁned (Figure 3-1).

Note: The 24C01SC/02SC does not generate

any acknowledge bits if an internal pro-

gramming cycle is in progress.

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

The device that acknowledges has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this case,

the slave must leave the data line HIGH to enable the

master to generate the STOP condition.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition. All

commands must be preceded by a START condition.

3.3

Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

DS21170A-page 4

Preliminary

1996 Microchip Technology Inc.

1 2 345 6 7...12

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与24C02ATE/SM相关器件

型号	品牌	描述	获取价格	数据表
24C02AT-E/SM	MICROCHIP	256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.207 INCH, PLASTIC, SOIC-8	获取价格
24C02B	MICROCHIP	1K/2K 5.0V I 2 C ⑩ Serial EEPROM	获取价格
24C02B-E/P	MICROCHIP	1K/2K 5.0V I2C⑩ Serial EEPROM	获取价格
24C02B-E/SN	MICROCHIP	1K/2K 5.0V I2C⑩ Serial EEPROM	获取价格
24C02B-EP	MICROCHIP	1K/2K 5.0V I 2 C ⑩ Serial EEPROM	获取价格
24C02B-ESN	MICROCHIP	1K/2K 5.0V I 2 C ⑩ Serial EEPROM	获取价格

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