Datasheet > 10M02SCU169C8G

10M02SCU169C8G

更新时间： 2024-02-15 08:56:13

品牌	Logo	应用领域
英特尔 - INTEL		时钟栅可编程逻辑
页数	文件大小	规格书
14页	604K
描述
Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-169

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10M02SCU169C8G 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	BGA,	Reach Compliance Code：	compliant
风险等级：	5.73	JESD-30 代码：	S-PBGA-B169
端子数量：	169	最高工作温度：	85 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	表面贴装：	YES
温度等级：	OTHER	端子形式：	BALL
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

10M02SCU169C8G 数据手册

M10-OVERVIEW

2014.09.22

Configuration

External Memory Interface⁽²⁾

I/O Standard

SSTL-18

Maximum Width

16 bit + 8 bit ECC

16 bit without ECC

Maximum Frequency (MHz)

DDR2 SDRAM

200

LPDDR2 SDRAM

HSUL-12

Note: MAX 10 FPGA support for the DDR3, DDR3L, DDR2, and LPDDR2 external memory interfaces is

not available by default in the Quartus II software. Contact your local sales representative for

support.

Related Information

External Memory Interface Spec Estimator

Provides a parametric tool that allows you to find and compare the performance of the supported external

memory interfaces in Altera devices.

Configuration

Table 12: Configuration Features

Feature

Description

Dual-image configuration

•

Stores two configuration images in the configuration flash memory

(CFM)

Selects the first configuration image to boot using the BOOT_SEL

Design security

•

Supports 128 bit key with non-volatile key programming

Limits access of the JTAG instruction during power-up in the JTAG

secure mode

SEU Mitigation⁽³⁾

•

Auto-detects cyclic redundancy check (CRC) errors during configu‐

ration

Provides optional CRC error detection and identification in user

mode.

Dual-purpose configuration pin

Configuration data compression

•

Functions as configuration pins prior to user mode

Provides option to be used as configuration pins or user I/O pins in

user mode

•

Receives compressed configuration bitstream and decompresses the

data in real-time during configuration

Reduces the configuration image size stored in the CFM

(2)

The device hardware supports SRAM. Use your own design to interface with SRAM devices.

The SEU mitigation feature for single supply devices is disabled by default in the Quartus II software. For

more information and support, contact your local sales representative.

(3)

MAX 10 FPGA Device Overview

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Altera Corporation

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与10M02SCU169C8G相关器件

型号	品牌	获取价格	描述	数据表
10M02SCU169I7G	INTEL	获取价格	Field Programmable Gate Array, 2000-Cell, CMOS, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS C
10M04DAU324A7	INTEL	获取价格	Field Programmable Gate Array, PBGA324, 15 X 15 MM, 0.80 MM PITCH, UBGA-324
10M04DFU324C8G	INTEL	获取价格	Field Programmable Gate Array, 4000-Cell, CMOS, PBGA324, 15 X 15 MM, 0.80 MM PITCH, ROHS C
10M04SAU169A7	INTEL	获取价格	Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, UBGA-169
10M04SAU169C8G	INTEL	获取价格	Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-16
10M04SCM153I7	INTEL	获取价格	Field Programmable Gate Array, PBGA153, 8 X 8 MM, 0.50 MM PITCH, MBGA-153
10M04SCU169C8G	INTEL	获取价格	Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-16
10M04SFM153A7G	INTEL	获取价格	Field Programmable Gate Array, PBGA153, 8 X 8 MM, 0.50 MM PITCH, ROHS COMPLIANT, MBGA-153
10M08DAF256I7G	INTEL	获取价格	Field Programmable Gate Array, 8000-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, ROHS COMP
10M08DAU324A7	INTEL	获取价格	Field Programmable Gate Array, PBGA324, 15 X 15 MM, 0.80 MM PITCH, UBGA-324

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