Datasheet > 10M02SCU169C8G

10M02SCU169C8G

更新时间： 2024-02-19 08:43:46

品牌	Logo	应用领域
英特尔 - INTEL		时钟栅可编程逻辑
页数	文件大小	规格书
14页	604K
描述
Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-169

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10M02SCU169C8G 技术参数

是否Rohs认证：	符合	生命周期：	Transferred
包装说明：	BGA,	Reach Compliance Code：	compliant
风险等级：	5.73	JESD-30 代码：	S-PBGA-B169
端子数量：	169	最高工作温度：	85 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	BGA	封装形状：	SQUARE
封装形式：	GRID ARRAY	峰值回流温度（摄氏度）：	NOT SPECIFIED
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	表面贴装：	YES
温度等级：	OTHER	端子形式：	BALL
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
Base Number Matches：	1

10M02SCU169C8G 数据手册

M10-OVERVIEW

2014.09.22

Embedded Memory Blocks

•

DSP IP cores:

•

Common DSP processing functions such as finite impulse response (FIR), fast Fourier transform

(FFT), and numerically controlled oscillator (NCO) functions

•

Suites of common video and image processing functions

•

Complete reference designs for end-market applications

DSP Builder interface tool between the Quartus II software and the MathWorks Simulink and

MATLAB design environments

•

DSP development kits

Embedded Memory Blocks

Each M9K memory block of the MAX 10 device provides 9 Kb of on-chip memory capable of operating at

up to 284 MHz. The embedded memory structure consists of M9K memory blocks columns. You can

configure the columns of the embedded M9K memory blocks as either one of the following:

•

RAM

First-in first-out (FIFO) buffers

ROM

The MAX 10 device memory blocks are optimized for applications such as high throughput packet

processing, embedded processor program, and embedded data storage.

You can utilize the M9K memory blocks using the following options:

•

Parameterize relevant IP cores with the Quartus II parameter editor

Infer the multipliers directly with VHDL or Verilog

Table 10: M9K Supported Operation Modes and Configurations

M9K Operation Modes

Port Widths Configuration

Single-port

×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36

×1, ×2, ×4, ×8, ×9, ×16, and ×18

Simple dual-port

True dual-port

Clocking and PLL

MAX 10 devices support up to 20 global clock (GCLK) networks with operating frequency up to

450 MHz. The GCLK networks have high drive strength and low skew.

MAX 10 devices have built-in internal oscillator.

The high precision and low jitter PLLs have the following usages:

MAX 10 FPGA Device Overview

Send Feedback

Altera Corporation

1...8 9 101112 13 14

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与10M02SCU169C8G相关器件

型号	品牌	获取价格	描述	数据表
10M02SCU169I7G	INTEL	获取价格	Field Programmable Gate Array, 2000-Cell, CMOS, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS C
10M04DAU324A7	INTEL	获取价格	Field Programmable Gate Array, PBGA324, 15 X 15 MM, 0.80 MM PITCH, UBGA-324
10M04DFU324C8G	INTEL	获取价格	Field Programmable Gate Array, 4000-Cell, CMOS, PBGA324, 15 X 15 MM, 0.80 MM PITCH, ROHS C
10M04SAU169A7	INTEL	获取价格	Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, UBGA-169
10M04SAU169C8G	INTEL	获取价格	Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-16
10M04SCM153I7	INTEL	获取价格	Field Programmable Gate Array, PBGA153, 8 X 8 MM, 0.50 MM PITCH, MBGA-153
10M04SCU169C8G	INTEL	获取价格	Field Programmable Gate Array, PBGA169, 11 X 11 MM, 0.80 MM PITCH, ROHS COMPLIANT, UBGA-16
10M04SFM153A7G	INTEL	获取价格	Field Programmable Gate Array, PBGA153, 8 X 8 MM, 0.50 MM PITCH, ROHS COMPLIANT, MBGA-153
10M08DAF256I7G	INTEL	获取价格	Field Programmable Gate Array, 8000-Cell, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, ROHS COMP
10M08DAU324A7	INTEL	获取价格	Field Programmable Gate Array, PBGA324, 15 X 15 MM, 0.80 MM PITCH, UBGA-324

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