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ZSSC3018BAC PDF预览

ZSSC3018BAC

更新时间： 2024-01-31 00:59:19
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
50页 1243K
描述
Analog Circuit

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ZSSC3018BAC 技术参数

是否Rohs认证： 不符合生命周期：Active
包装说明：UUC,Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.57
模拟集成电路 - 其他类型：ANALOG CIRCUITJESD-30 代码：R-XUCC-N
信道数量：1功能数量：1
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：UUC
封装形状：RECTANGULAR封装形式：UNCASED CHIP
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.68 V
标称供电电压 (Vsup)：1.8 V表面贴装：NO
技术：CMOS温度等级：AUTOMOTIVE
端子形式：NO LEAD端子位置：UNSPECIFIED
Base Number Matches：1

ZSSC3018BAC 数据手册

 浏览型号ZSSC3018BAC的Datasheet PDF文件第3页浏览型号ZSSC3018BAC的Datasheet PDF文件第4页浏览型号ZSSC3018BAC的Datasheet PDF文件第5页浏览型号ZSSC3018BAC的Datasheet PDF文件第7页浏览型号ZSSC3018BAC的Datasheet PDF文件第8页浏览型号ZSSC3018BAC的Datasheet PDF文件第9页 
ZSSC3018 Datasheet  
1. IC Characteristics  
1.1 Absolute Maximum Ratings  
Note: The absolute maximum ratings are stress ratings only. The ZSSC3018 might not function or be operable above the recommended  
operating conditions. Stresses exceeding the absolute maximum ratings might also damage the device. In addition, extended exposure to  
stresses above the recommended operating conditions might affect device reliability. IDT does not recommend designing to the “Absolute  
Maximum Ratings.”  
Table 1.1 Absolute Maximum Ratings  
PARAMETER  
SYMBOL  
Vss  
Min  
0
TYP  
MAX  
0
UNITS  
Voltage Reference  
V
V
Analog Supply Voltage  
VDD  
-0.4  
-0.5  
-100  
3.63  
VDD+0.5  
100  
Voltage at all Analog and Digital IO Pins  
VA_IO, VD_IO  
IIN  
V
Input Current into any Pin except RES, TEST1, TEST2, TEST3, TEST4,  
TEST5, and SS [a], [b]  
mA  
Electrostatic Discharge Tolerance – Human Body Model (HBM1) [c]  
VHBM1  
TSTOR  
4000  
-50  
-
V
Storage Temperature  
130  
°C  
[a] Latch-up current limit for RES, TEST1, TEST2, TEST3, TEST4, TEST5, and SS: ±70mA.  
[b] Latch-up resistance; reference for pin is 0V.  
[c] HBM1: C = 100pF charged to VHBM1 with resistor R = 1.5kin series based on MIL 883, Method 3015.7. ESD protection  
referring to the Human Body Model is tested with devices in ceramic dual in-line packages (CDIP) during product qualification.  
1.2 Operating Conditions  
Note: The reference for all voltages is Vss.  
Table 1.2 Operating Conditions  
PARAMETER  
SYMBOL  
VDD  
MIN  
TYP  
MAX  
3.6  
UNIT  
V
Supply Voltage  
VDD Rise Time  
1.68  
-
tVDD  
200  
1.8  
μs  
Bridge Current [a]  
IVDDB  
mA  
16.5  
125  
50  
Operation Temperature Range  
TAMB  
CL  
-40  
-
°C  
nF  
External (parasitic) Capacitance between VDDB and VSS  
0.01  
[a] Power supply rejection is reduced if a current in the range of 16.5mA > IVDDB > 1.8mA is drawn out of VDDB.  
A dynamic power-on-reset circuit is implemented in order to achieve the minimum current consumption in Sleep Mode. The VDD low level,  
the subsequent rise time, and the VDD rising slope must meet the requirements in Table 1.3 to guarantee an overall IC reset: lower VDD low  
levels allow slower rising of the subsequent on-ramp of VDD. Other combinations might also be possible. For example, the reset trigger can  
be influenced by increasing the power-down time and lowering the VDD rising slope requirement. Alternatively, the RES pin can be connected  
and used to control safe resetting of the IC. RES is low-active – a VDD-VSS-VDD transition at the RES pin leads to a complete ZSSC3018  
reset.  
© 2016 Integrated Device Technology, Inc  
6
November 14, 2016  
 
 
 
 
 
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