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ZL50073GA PDF预览

ZL50073GA

更新时间: 2024-02-24 15:18:01
品牌 Logo 应用领域
加拿大卓联 - ZARLINK 开关
页数 文件大小 规格书
67页 612K
描述
Digital Time Switch, PBGA484, 23 X 23 MM, 1 MM PITCH, PLASTIC, BGA-484

ZL50073GA 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:484
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.53JESD-30 代码:S-PBGA-B484
JESD-609代码:e0长度:23 mm
功能数量:1端子数量:484
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):225认证状态:Not Qualified
座面最大高度:2.16 mm标称供电电压:1.8 V
表面贴装:YES电信集成电路类型:DIGITAL TIME SWITCH
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:23 mmBase Number Matches:1

ZL50073GA 数据手册

 浏览型号ZL50073GA的Datasheet PDF文件第60页浏览型号ZL50073GA的Datasheet PDF文件第61页浏览型号ZL50073GA的Datasheet PDF文件第62页浏览型号ZL50073GA的Datasheet PDF文件第64页浏览型号ZL50073GA的Datasheet PDF文件第65页浏览型号ZL50073GA的Datasheet PDF文件第66页 
ZL50073  
Data Sheet  
AC Electrical Characteristics - Microprocessor Bus Interface  
No  
Characteristics (Figure , & Figure 20)  
Sym. Min. Typ.1 Max. Units  
Notes  
tDSRE  
tCSRE  
tCSS  
1
2
3
4
5
6
DS Recovery  
5
0
0
0
0
0
ns  
ns  
ns  
ns  
ns  
ns  
CS Recovery  
CS asserted setup to DS asserted  
Address, SIZ1-0, R/W setup to DS asserted  
CS hold from DS deasserted  
tADS  
tCSH  
tADH  
Address, SIZ0-1, R/W hold from DS  
deasserted  
tDSR  
tDZ  
7
8
Data valid to DTA asserted on read  
0
ns  
ns  
CL = 50 pF,  
RL = 1 k2  
CS deasserted to Data tri-stated on read  
5
9
CL = 50 pF,  
RL = 1 k2  
tWDS  
9
Data setup to DS asserted on write  
CS asserted to WAIT deasserted  
0
0
ns  
ns  
tCSWA  
10  
CL = 30 pF,  
RL = 1K2  
tDHW  
tWDD  
11  
12  
Data hold from DTA asserted on write  
DS asserted to WAIT Asserted  
ns  
ns  
9
10  
155  
75  
7
CL = 50 pF,  
RL = 1 k2  
tAKS  
tAKD  
13  
14  
WAIT deasserted to DTA/BERR asserted  
skew  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
CL = 50 pF,  
RL = 1 k2  
DS asserted to DTA Asserted  
35  
50  
Connection  
Memory  
All other  
registers  
tAKH  
tDTHZ  
tWAHZ  
15  
16  
17  
DS deasserted to DTA Deasserted  
CS deasserted to DTA tri-stated  
CS deasserted to WAIT tri-stated  
CL = 30 pF,  
RL = 1K2  
13  
6
CL = 30 pF,  
RL = 1 K2  
CL = 30 pF,  
RL = 1K2  
tDSK  
18  
19  
BE or UDS/LDS skew  
20  
tBEDS  
BE or UDS/LDS to DS set-up  
0
Note 1: Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not  
subject to production testing.  
Note 2: High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge  
CL.  
63  
Zarlink Semiconductor Inc.  

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