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ZL50114 PDF预览

ZL50114

更新时间: 2024-02-21 11:50:20
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
103页 1192K
描述
128, 256 and 1024 Channel CESoP Processors

ZL50114 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:BGA, BGA552,26X26,50Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.73
JESD-30 代码:S-PBGA-B552JESD-609代码:e0
长度:35 mm湿度敏感等级:1
功能数量:1端子数量:552
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装等效代码:BGA552,26X26,50封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
电源:1.8,3.3 V认证状态:Not Qualified
座面最大高度:2.53 mm子类别:Other Telecom ICs
标称供电电压:1.8 V表面贴装:YES
电信集成电路类型:TELECOM CIRCUIT温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:30宽度:35 mm
Base Number Matches:1

ZL50114 数据手册

 浏览型号ZL50114的Datasheet PDF文件第2页浏览型号ZL50114的Datasheet PDF文件第3页浏览型号ZL50114的Datasheet PDF文件第4页浏览型号ZL50114的Datasheet PDF文件第5页浏览型号ZL50114的Datasheet PDF文件第6页浏览型号ZL50114的Datasheet PDF文件第7页 
ZL50110/11/14  
128, 256 and 1024 Channel CESoP  
Processors  
Data Sheet  
October 2006  
Features  
Ordering Information  
General  
ZL50110GAG  
ZL50111GAG  
ZL50114GAG  
552 PBGA  
552 PBGA  
552 PBGA  
Trays, Bake & Drypack  
Trays, Bake & Drypack  
Trays, Bake & Drypack  
Circuit Emulation Services over Packet (CESoP)  
transport for MPLS, IP and Ethernet networks  
ZL50110GAG2 552 PBGA** Trays, Bake & Drypack  
ZL50111GAG2 552 PBGA** Trays, Bake & Drypack  
ZL50114GAG2 552 PBGA** Trays, Bake & Drypack  
On chip timing & synchronization recovery across  
a packet network  
**Pb Fee Tin Silver/Copper  
Grooming capability for Nx64 Kbps trunking  
-40°C to +85°C  
Circuit Emulation Services  
Direct connection to LIUs, framers, backplanes  
Complies with ITU-T recommendation Y.1413  
Dual reference Stratum 3, 4 and 4E DPLL for  
synchronous operation  
Complies with IETF PWE3 draft standards for  
CESoPSN and SAToP  
Network Interfaces  
Complies with CESoP draft IAs for MEF and MFA  
Up to 3 x 100 Mbps MII Fast Ethernet or Dual  
Redundant 1000 Mbps GMII/TBI Ethernet  
Interfaces  
Structured, synchronous CESoP with clock  
recovery  
Unstructured, asynchronous CESoP, with integral  
per stream clock recovery  
System Interfaces  
TDM Interfaces  
Flexible 32 bit host CPU interface (Motorola  
PowerQUICCcompatible)  
Up to 32 T1/E1, 8 J2, 2 T3/E3 or 1 STS-1 ports  
H.110, H-MVIP, ST-BUS backplanes  
Up to 1024 bi-directional 64 Kbps channels  
On-chip packet memory for self-contained  
operation, with buffer depths of over 16 ms  
Up to 8 Mbytes of off-chip packet memory,  
supporting buffer depths of over 128 ms  
Multi-Protocol  
Packet  
TDM  
Interface  
Triple  
Packet  
Interface  
MAC  
Processing  
Engine  
(LIU, Framer, Backplane)  
PW, RTP, UDP,  
IPv4, IPv6, MPLS,  
ECID, VLAN, User  
Defined, Others  
Per Port DCO for  
Clock Recovery  
(MII, GMII, TBI)  
On Chip Packet Memory  
(Jitter Buffer Compensation for 16-128 ms of Packet Delay Variation)  
Dual Reference  
Stratum 3 DPLL  
Host Processor  
Interface  
External Memory  
Interface (optional)  
32-bit Motorola compatible  
DMA for signaling packets  
ZBT-SRAM  
(0 - 8 Mbytes)  
Figure 1 - ZL50110/11/14 High Level Overview  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2003-2006, Zarlink Semiconductor Inc. All Rights Reserved.  

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