Datasheet > ZL50112

ZL50112

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
加拿大卓联 - ZARLINK		/
页数	文件大小	规格书
112页	1041K
描述
128, 256, 512 and 1024 Channel CESoP Processors

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数据手册

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ZL50112 数据手册

ZL50110/11/12/14

128, 256, 512 and 1024 Channel CESoP

Processors

Data Sheet

April 2008

Features

Ordering Information

General

ZL50110GAG

ZL50111GAG

ZL50112GAG

ZL50114GAG

552 PBGA

Trays, Bake & Drypack

•

Circuit Emulation Services over Packet (CESoP)

transport for MPLS, IP and Ethernet networks

ZL50110GAG2 552 PBGA** Trays, Bake & Drypack

ZL50111GAG2 552 PBGA** Trays, Bake & Drypack

ZL50112GAG2 552 PBGA** Trays, Bake & Drypack

ZL50114GAG2 552 PBGA** Trays, Bake & Drypack

On chip timing & synchronization recovery across

a packet network

Grooming capability for Nx64 Kbps trunking

**Pb Fee Tin Silver/Copper

-40°C to +85°C

Circuit Emulation Services

•

Supports ITU-T Recommendation Y.1413 and

Y.1453

•

Direct connection to LIUs, framers, backplanes

Dual reference Stratum 4 and 4E DPLL for

synchronous operation

•

Supports IETF RFC4553 and RFC5086

Supports MEF8 and MFA 8.0.0

Network Interfaces

Structured, synchronous CESoP with clock

recovery

•

Up to 3 x 100 Mbps MII Fast Ethernet or Dual

Redundant 1000 Mbps GMII/TBI Ethernet

Interfaces

•

Unstructured, asynchronous CESoP, with integral

per stream clock recovery

System Interfaces

TDM Interfaces

•

Flexible 32 bit host CPU interface (Motorola

PowerQUICC^™compatible)

•

Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports

H.110, H-MVIP, ST-BUS backplanes

Up to 1024 bi-directional 64 Kbps channels

On-chip packet memory for self-contained

operation, with buffer depths of over 16 ms

Up to 8 Mbytes of off-chip packet memory,

supporting buffer depths of over 128 ms

M ulti-Protocol

Packet

Processing

Engine

TDM

Interface

Triple

Packet

Interface

M AC

(LIU, Framer, Backplane)

PW , RTP, UDP,

IPv4, IPv6, MPLS,

ECID, VLAN, User

Defined, Others

(M II, GM II, TBI)

Per Port DCO for

Clock Recovery

On Chip Packet Mem ory

(Jitter Buffer Com pensation for 16-128 m s of Packet Delay Variation)

Dual Reference

Stratum 3 DPLL

Host Processor

Interface

External Mem ory

Interface (optional)

32-bit Motorola com patible

DMA for signaling packets

ZBT-SRAM

(0 - 8 Mbytes)

Figure 1 - ZL50111 High Level Overview

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

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与ZL50112相关器件

型号	品牌	描述	获取价格	数据表
ZL50112GAG	ZARLINK	128, 256, 512 and 1024 Channel CESoP Processors	获取价格
ZL50112GAG2	ZARLINK	128, 256, 512 and 1024 Channel CESoP Processors	获取价格
ZL50112GAG2	MICROSEMI	Telecom Circuit, 1-Func, PBGA552, 35 X 35 MM, 1.27 MM, LEAD FREE, PLASTIC, BGA-552	获取价格
ZL50114	ZARLINK	128, 256 and 1024 Channel CESoP Processors	获取价格
ZL50114GAG	ZARLINK	128, 256 and 1024 Channel CESoP Processors	获取价格
ZL50114GAG	MICROSEMI	Telecom Circuit, 1-Func, PBGA552, 35 X 35 MM, 1.27 MM PITCH, PLASTIC, MS-034BAR-2, BGA-552	获取价格