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ZL30673 PDF预览

ZL30673

更新时间: 2024-11-24 02:50:31
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
6页 361K
描述
1-, 2-, 3-Channel, 10-Input, 18-Output System Synchronizers

ZL30673 数据手册

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ZL30671, ZL30672, ZL30673  
1-, 2-, 3-Channel, 10-Input, 18-Output  
System Synchronizers  
Product Brief  
November 2019  
Features  
Ordering Information  
One, Two or Three DPLL Channels  
ZL30671LFG7 1-Channel 80-lead LGA Trays  
ZL30672LFG7 2-Channel 80-lead LGA Trays  
ZL30673LFG7 3-Channel 80-lead LGA Trays  
Timing compliance with ITU-T G.8262, G.813,  
G.812, G.8273.2; Telcordia GR-1244, GR-253  
NiAu (Pb-free)  
Programmable bandwidth, 0.1mHz to 470Hz  
Freerun or holdover on loss of all inputs  
Hitless reference switching  
Package size: 11 x 11 mm  
-40 C to +85 C  
Per-output programmable duty cycle  
High-resolution holdover averaging  
Precise output alignment circuitry and per-  
Per-DPLL phase adjustment, 1ps resolution  
output phase adjustment  
Programmable tracking range, phase-slope  
limiting, frequency-change limiting and other  
advanced features  
Per-output enable/disable and glitchless  
start/stop (stop high or low)  
Local Oscillator  
Input Clocks  
Operates from a single TCXO or OCXO: 23.75-  
Accepts up to 10 differential or CMOS inputs  
Any input frequency from 0.5Hz to 900MHz  
Per-input activity and frequency monitoring  
Automatic or manual reference switching  
25MHz, 47.5-50MHz, 114.285-125MHz  
Very-low-jitter applications can connect a TCXO  
or OCXO as the stability reference and a low-  
jitter XO as the jitter reference  
Revertive or nonrevertive switching  
General Features  
Any input can be a 1PPS SYNC input for  
Automatic self-configuration at power-up from  
REF+SYNC frequency/phase/time locking  
internal Flash memory  
Input-input phase measurement, 1ps resolution  
Input-DPLL phase measurement, 1ps resolution  
Per-input phase adjustment, 1ps resolution  
Input-to-output alignment <200ps (ext feedback)  
Fast REF+SYNC locking for frequency and  
1PPS phase alignment with lower-cost oscillator  
Internal compensation (1ppt) for local oscillator  
Output Clock Frequency Generation  
frequency error in DPLLs and input monitors  
Any output frequency from <0.5Hz to 1045MHz  
Numerically controlled oscillator behavior in  
(180MHz max for Synth0)  
each DPLL and each fractional output divider  
High-resolution fractional frequency conversion  
Easy-to-configure design requires no external  
with 0ppm error  
VCXO or loop filter components  
Synthesizers 1 & 2 have integer and fractional  
7 GPIO pins with many possible behaviors  
SPI or I2C processor Interface  
dividers to make a total of 5 frequency families  
Output jitter from Synth 1 & 2 is <0.3ps RMS  
1.8V and 3.3V core VDD voltages  
Output jitter from fractional dividers is typically  
< 1ps RMS, many frequencies <0.5ps RMS  
Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out  
Easy-to-use evaluation/programming software  
Each HPOUTP/N pair can be LVDS, LVPECL,  
HCSL, 2xCMOS, HSTL or programmable diff.  
Applications  
In 2xCMOS mode, the P and N pins can be  
different frequencies (e.g. 125MHz and 25MHz)  
Central system timing ICs for SyncE,  
SyncE+1588, SONET/SDH, OTN, wireless  
base station and other carrier-grade systems  
G.8262/813 EEC/SEC, Telcordia Stratum 2-4  
Four output banks each with VDDO pin; CMOS  
output voltages from 1.5V to 3.3V  
Per-synthesizer phase adjust, 1ps resolution  
1
Microsemi Confidential  
Copyright 2019. Microsemi Corporation. All Rights Reserved.  

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