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ZL30661LFG7 PDF预览

ZL30661LFG7

更新时间: 2024-11-07 02:50:03
品牌 Logo 应用领域
美高森美 - MICROSEMI /
页数 文件大小 规格书
5页 290K
描述
1-, 2-, 3-Channel, 10-Input, 18-Output Line Card Timing ICs

ZL30661LFG7 数据手册

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ZL30661, ZL30662, ZL30663  
1-, 2-, 3-Channel, 10-Input, 18-Output  
Line Card Timing ICs  
Product Brief  
August 2019  
Features  
Ordering Information  
One, Two or Three DPLL Channels  
Programmable bandwidth, 14Hz to 470Hz  
Freerun or holdover on loss of all inputs  
Hitless reference switching  
ZL30661LFG7 1-Channel 80-lead LGA Trays  
ZL30662LFG7 2-Channel 80-lead LGA Trays  
ZL30663LFG7 3-Channel 80-lead LGA Trays  
NiAu (Pb-free)  
Package size: 11 x 11 mm  
High-resolution holdover averaging  
-40 C to +85 C  
Per-DPLL phase adjustment, 1ps resolution  
Per-output programmable duty cycle  
Programmable tracking range, phase-slope  
limiting, frequency-change limiting and other  
advanced features  
Precise output alignment circuitry and per-  
output phase adjustment  
Per-output enable/disable and glitchless  
Input Clocks  
start/stop (stop high or low)  
Accepts up to 10 differential or CMOS inputs  
Any input frequency from 1kHz to 900MHz  
Per-input activity and frequency monitoring  
Automatic or manual reference switching  
Local Oscillator  
Operates from a single low-cost XO: 23.75-  
25MHz, 47.5-50MHz, 114.285-125MHz  
High-stability applications can connect a TCXO  
or OCXO (any frequency, any output jitter) to  
the OSCI pin to provide a stability reference  
Revertive or nonrevertive switching  
Any input can be a 1PPS SYNC input for  
REF+SYNC frequency/phase/time locking  
General Features  
Any input can be a clock with embedded 1PPS  
Input-input phase measurement, 1ps resolution  
Input-DPLL phase measurement, 1ps resolution  
Per-input phase adjustment, 1ps resolution  
Automatic self-configuration at power-up from  
internal Flash memory  
Input-to-output alignment <200ps (ext feedback)  
Fast REF+SYNC locking for frequency and  
1PPS phase alignment with lower-cost oscillator  
Output Clock Frequency Generation  
Internal compensation (1ppt) for local oscillator  
Any output frequency from <1Hz to 1045MHz  
frequency error in DPLLs and input monitors  
(180MHz max for Synth0)  
Numerically controlled oscillator behavior in  
High-resolution fractional frequency conversion  
each DPLL and each fractional output divider  
with 0ppm error  
Easy-to-configure design requires no external  
Synthesizers 1 & 2 have integer and fractional  
VCXO or loop filter components  
dividers to make a total of 5 frequency families  
7 GPIO pins with many possible behaviors  
SPI or I2C processor Interface  
Output jitter from Synth 1 & 2 is <0.3ps RMS  
Output jitter from fractional dividers is typically  
1.8V and 3.3V core VDD voltages  
< 1ps RMS, many frequencies <0.5ps RMS  
Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out  
Easy-to-use evaluation/programming software  
Each HPOUTP/N pair can be LVDS, LVPECL,  
HCSL, 2xCMOS, HSTL or programmable diff.  
In 2xCMOS mode, the P and N pins can be  
Applications  
different frequencies (e.g. 125MHz and 25MHz)  
Line card timing IC for SyncE, SyncE+1588,  
SONET/SDH, OTN, wireless base station and  
other systems carrier-grade system  
Four output banks each with VDDO pin; CMOS  
output voltages from 1.5V to 3.3V  
Per-synthesizer phase adjust, 1ps resolution  
1
Microsemi Confidential  
Copyright 2019. Microsemi Corporation. All Rights Reserved.  

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