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Z8L18020PSC PDF预览

Z8L18020PSC

更新时间: 2024-10-27 07:42:03
品牌 Logo 应用领域
ZILOG 微控制器和处理器外围集成电路微处理器光电二极管时钟
页数 文件大小 规格书
70页 386K
描述
ENHANCED Z180 MICROPROCESSOR

Z8L18020PSC 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:DIP
包装说明:SDIP, SDIP64,.75针数:64
Reach Compliance Code:unknownECCN代码:3A001.A.2.C
HTS代码:8542.31.00.01风险等级:5.55
Is Samacsys:N其他特性:ALSO OPERATES AT 3.3V SUPPLY
地址总线宽度:19位大小:8
边界扫描:NO最大时钟频率:20 MHz
外部数据总线宽度:8格式:FIXED POINT
集成缓存:NOJESD-30 代码:R-PDIP-T64
JESD-609代码:e0长度:57.785 mm
低功率模式:YES端子数量:64
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SDIP
封装等效代码:SDIP64,.75封装形状:RECTANGULAR
封装形式:IN-LINE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3/5 V认证状态:Not Qualified
座面最大高度:5.01 mm速度:20 MHz
子类别:Microprocessors最大压摆率:60 mA
最大供电电压:5.5 V最小供电电压:4.5 V
标称供电电压:5 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:1.78 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:19.05 mm
uPs/uCs/外围集成电路类型:MICROPROCESSORBase Number Matches:1

Z8L18020PSC 数据手册

 浏览型号Z8L18020PSC的Datasheet PDF文件第2页浏览型号Z8L18020PSC的Datasheet PDF文件第3页浏览型号Z8L18020PSC的Datasheet PDF文件第4页浏览型号Z8L18020PSC的Datasheet PDF文件第5页浏览型号Z8L18020PSC的Datasheet PDF文件第6页浏览型号Z8L18020PSC的Datasheet PDF文件第7页 
PRELIMINARY PRODUCT SPECIFICATION  
1
Z80180/Z8S180/  
1
Z8L180 SL1919  
ENHANCED Z180 MICROPROCESSOR  
FEATURES  
®
Code Compatible with Zilog Z80 CPU  
Two 16-Bit Counter/Timers  
Extended Instructions  
Two Enhanced UARTs (up to 512 Kbps)  
Clock Speeds: 6, 8, 10, 20, 33 MHz  
Operating Range: 5V (3.3V@ 20 MHz)  
Two Chain-Linked DMA Channels  
Low Power-Down Modes  
°
°
On-Chip Interrupt Controllers  
Three On-Chip Wait-State Generators  
On-Chip Oscillator/Generator  
Expanded MMU Addressing (up to 1 MB)  
Clocked Serial I/O Port  
Operating Temperature Range: 0 C to +70 C  
°
°
-40 C to +85 C Extended Temperature Range  
Three Packaging Styles  
68-Pin PLCC  
64-Pin DIP  
80-Pin QFP  
GENERAL DESCRIPTION  
The enhanced Z80180/Z8S180/Z8L180 significantly im-  
Not only does the Z80180/Z8S180/Z8L180 consume less  
power during normal operations than the previous model,  
it has also been designed with three modes intended to fur-  
proves on the previous Z80180 models while still providing  
full backward compatibility with existing Zilog Z80 devices.  
The Z80180/Z8S180/Z8L180 now offers faster execution  
speeds, power saving modes, and EMI noise reduction.  
ther reduce the power consumption. Zilog reduced I pow-  
cc  
er consumption during STANDBY Mode to a minimum of  
10 µA by stopping the external oscillators and internal  
clock. The SLEEP mode reduces power by placing the  
CPU into a “stopped” state, thereby consuming less cur-  
rent while the on-chip I/O device is still operating. The  
SYSTEM STOP mode places both the CPU and the on-  
chip peripherals into a “stopped” mode, thereby reducing  
power consumption even further.  
This enhanced Z180 design also incorporates additional  
feature enhancements to the ASCIs, DMAs, and I  
cc  
STANDBY Mode power consumption. With the addition of  
“ESCC-like” Baud Rate Generators (BRGs), the two ASCIs  
now have the flexibility and capability to transfer data asyn-  
chronously at rates of up to 512 Kbps. In addition, the ASCI  
receiver has added a 4-byte First In First Out (FIFO) which  
can be used to buffer incoming data to reduce the inci-  
dence of overrun errors. The DMAs have been modified to  
allow for a “chain-linking” of the two DMA channels when  
set to take their DMA requests from the same peripherals  
device. This feature allows for non-stop DMA operation be-  
tween the two DMA channels, reducing the amount of CPU  
intervention (Figure 1).  
A new clock doubler feature has been implemented in the  
Z80180/Z8S180/Z8L180 device that allows the program-  
mer to double the internal clock from that of the external  
clock. This provides a systems cost savings by allowing  
the use of lower cost, lower frequency crystals instead of  
the higher cost, and higher speed oscillators.  
The Enhanced Z180 is housed in 80-pin QFP, 68-pin  
PLCC, and 64-pin DIP packages.  
DS971800401  
P R E L I M I N A R Y  
1-1  

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