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Z8L18020VSC PDF预览

Z8L18020VSC

更新时间: 2024-10-27 20:26:15
品牌 Logo 应用领域
IXYS 外围集成电路
页数 文件大小 规格书
71页 531K
描述
RISC Microprocessor, 8-Bit, 20MHz, CMOS, PQCC68,

Z8L18020VSC 技术参数

是否Rohs认证: 不符合生命周期:Active
包装说明:QCCJ, LDCC68,1.0SQReach Compliance Code:unknown
风险等级:5.87Is Samacsys:N
位大小:8JESD-30 代码:S-PQCC-J68
端子数量:68最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC68,1.0SQ
封装形状:SQUARE封装形式:CHIP CARRIER
电源:3.3/5 V认证状态:Not Qualified
速度:20 MHz子类别:Microprocessors
最大压摆率:50 mA表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:QUADuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

Z8L18020VSC 数据手册

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Code Compatible with ZiLOG Z80 CPU  
Extended Instructions  
Two 16-Bit Counter/Timers  
Two Enhanced UARTs (up to 512 Kbps)  
Clock Speeds: 10, 20, 33 MHz  
Two Chain-Linked DMA Channels  
Low Power-Down Modes  
Operating Range: 5V (3.3V@ 20 MHz)  
Operating Temperature Range: 0°C to +70°C  
–40°C to +85°C Extended Temperature Range  
Three Packaging Styles  
On-Chip Interrupt Controllers  
Three On-Chip Wait-State Generators  
On-Chip Oscillator/Generator  
Expanded MMU Addressing (Up to 1 MB)  
Clocked Serial I/O Port  
68-Pin PLCC  
64-Pin DIP  
80-Pin QFP  
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three modes intended to further reduce power consumption.  
Power consumption during 56#0&$; Mode is reduced to  
10 µA by stopping the external oscillators and internal  
clock. The 5.''2 mode reduces power by placing the CPU  
into a stopped state, consuming less current while the on-  
chip I/O devices still operate. The 5;56'/ꢅ5612 mode  
places both the CPU and the on-chip peripherals into a  
stopped mode, reducing power consumption even further.  
The enhanced Z8S180/Z8L180 significantly improves on  
previous Z80180 models, while still providing full back-  
ward compatibility with existing ZiLOG Z80 devices. The  
Z8S180/Z8L180 now offers faster execution speeds, pow-  
er-saving modes, and EMI noise reduction.  
This enhanced Z180 design also incorporates additional  
feature enhancements to the ASCIs, DMAs, and 56#0&$;  
mode power consumption. With the addition of ESCC-like  
BaudRateGenerators(BRGs),thetwoASCIsoffertheflex-  
ibility and capability to transfer data asynchronously atrates  
of up to 512 Kbps. In addition, the ASCI receiver features  
a 4-byte first in/first out (FIFO) buffer which reduces the  
likelihoodofoverrunerrors.TheDMAshavebeenmodified  
to allow for chain-linking of the two DMA channels when  
set to take their DMA requests from the same peripherals  
device. This feature allows for nonstop DMA operation be-  
tween the two DMA channels.  
A new clock-doubler feature in the Z8S180/Z8L180 allows  
the internal clock speed to be twice the external clock speed.  
As a result, system cost is reduced by allowing the use of  
lower-cost, lower-frequency crystals.  
The Enhanced Z180 is housed in 80-pin QFP, 68-pin PLCC,  
and 64-pin DIP packages.  
0QVGꢅ All Signals with an overline are active Low. For exam-  
ple: B/W, in which WORD is active Low; or B/W, in  
which BYTE is active Low.  
NotonlydoestheZ8S180/Z8L180consumelesspowerdur-  
ing normal operations than the previous model, it offers  
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