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Z8523316ASG PDF预览

Z8523316ASG

更新时间: 2024-11-04 20:45:51
品牌 Logo 应用领域
ZILOG /
页数 文件大小 规格书
19页 402K
描述
Micro Peripheral IC,

Z8523316ASG 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:QFP
包装说明:,Reach Compliance Code:unknown
风险等级:8.35JESD-609代码:e3
湿度敏感等级:3端子面层:Matte Tin (Sn)
Base Number Matches:1

Z8523316ASG 数据手册

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CUSTOMER PROCUREMENT SPECIFICATION  
Z85233  
EMSCCENHANCED MONO  
SERIAL COMMUNICATION CONTROLLER  
GENERAL DESCRIPTION  
The Zilog Enhanced Mono SerialCommunication Controller,  
Z85233 EMSCC, is a software compatible CMOS member  
of the SCC family introduced by Zilog in 1981. The EMSCC  
is a full-duplex data communications controller capable of  
supporting a wide range of popular protocols. The Z85233  
EMSCC is a single channel version (Channel A) of Zilog's  
Z85230 ESCC. Based on ZIlog's unique Superintegration™  
Technology, the EMSCC is compatible with designs using  
Zilog's SCC and ESCC to receive and transmit data. It has  
many improvements that significantly reduce CPU  
overhead. The addition of a 4-byte transmit FIFO and an  
8-byte receive FIFO significantly reduces the overhead  
required to provide data to, and getdata from, the transmitter  
and receiver.  
The CPU hardware interface has been simplified by reliev-  
ing the databus setup time requirement and supporting  
the software generation of the interrupt acknowledge  
signal (/INTACK). These changes allow an interface with  
less external logic to many microprocessor families while  
maintaining compatibility with existing designs. I/O han-  
dling of the EMSCC is improved over the SCC with faster  
response of the /INT and /DTR//REQ pins.  
The many enhancements added to the EMSCC permits a  
system design that increases overall system performance  
with better data handling and less interface logic.  
Notes:  
All Signals with a preceding front slash, "/", are active Low, e.g.:  
B//W (WORD is active Low); /B/W (BYTE is active Low, only).  
The EMSCC also has many features that improve packet  
handling in SDLC mode. The EMSCC will automatically:  
transmit a flag before the data, reset the Tx Underrun/EOM  
latch, force the TxD pin high at the appropriate time when  
using NRZI encoding, deassert the /RTS pin after the  
closing flag, and better handle ABORTed frames when  
using the 10x19 status FIFO. The combination of these  
features along with the deeper data FIFOs significantly  
simplifies SDLC driver software.  
Power connections follow conventional descriptions below:  
Connection  
Circuit  
Device  
Power  
VCC  
VDD  
Ground  
GND  
V
SS  
1
DC 4058-03  
(11-4-94)  

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