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Z8523316VSG PDF预览

Z8523316VSG

更新时间： 2024-09-15 12:47:23
品牌 Logo 应用领域
ZILOG 通信控制器外围集成电路先进先出芯片数据传输时钟
页数 文件大小 规格书
4页 58K
描述
EMSCC™ Enhanced Mono Serial Communication Controller

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中文翻译

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Z8523316VSG 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：LCC
包装说明：QCCJ,针数：44
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.71其他特性：MODEM CONTROL I/OS USABLE AS GENERAL PURPOSE I/OS; 10 X 19 FRAME STATUS FIFO
地址总线宽度：边界扫描：NO
最大时钟频率：16.384 MHz通信协议：ASYNC, BIT; SYNC, BYTE; SYNC, HDLC; SYNC, SDLC; X.25; BISYNC; EXT SYNC
数据编码/解码方法：NRZ; NRZI-SPACE; BIPH-MARK(FM1); BIPH-SPACE(FM0); BIPH-LEVEL(MANCHESTER)最大数据传输速率：0.512 MBps
外部数据总线宽度：8JESD-30 代码：S-PQCC-J44
JESD-609代码：e3长度：16.5862 mm
低功率模式：NODMA 通道数量：
I/O 线路数量：串行 I/O 数：1
端子数量：44片上数据RAM宽度：
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：260认证状态：Not Qualified
RAM（字数）：0座面最大高度：4.57 mm
最大压摆率：10 mA最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：MATTE TIN
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：16.5862 mmuPs/uCs/外围集成电路类型：SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches：1

Z8523316VSG 数据手册

 浏览型号Z8523316VSG的Datasheet PDF文件第2页浏览型号Z8523316VSG的Datasheet PDF文件第3页浏览型号Z8523316VSG的Datasheet PDF文件第4页 
EMSCC™ Enhanced Mono Serial Communication Controller  
Z85233  
Product Brief  
PB005802-0608  
•
•
New Programmable Features Added with  
Write Register 7'  
FEATURES  
•
Hardware and software compatible with  
Zilog's SCC/ ESCC™  
Write registers: WR3, WR4, WR5, and WR10  
are Now Readable  
•
Deeper Data FIFOs  
•
•
•
Read Register 0 Latched During Access  
Software Interrupt Acknowledge Mode  
–
–
4-Byte Transmit FIFO  
8-Byte Receive FIFO  
DPLL Counter Output Available as Jitter-Free  
Clock Source  
•
•
Programmable FIFO Interrupt Levels Provide  
Flexible Interrupt Response  
•
•
/DTR//REQ Pin Deactivation Time Reduced  
Many Improvements toSupport SDLC/  
HDLCTransfers:  
A Full-Duplex Channel with a Crystal Oscilla-  
tor, Baud Rate Generator, and Digital Phase-  
Locked Loop.  
–
–
–
Deactivation of /RTS Pin after Closing  
Flag  
Automatic Transmission of the Opening  
Flag  
•
•
Multi-Protocol Operation Under Program Con-  
trol  
Automatic Reset of Tx Underrun/EOM  
Latch  
Asynchronous Mode/Synchronous Mode  
–
–
Complete CRC Reception  
GENERAL DESCRIPTION  
TxD pin Automatically Forced High with  
NRZI Encoding when Using Mark Idle.  
The Zilog Enhanced Mono Serial Communication-  
Controller, Z85233 EMSCC, is a software compat-  
ible CMOS member of the SCC family introduced  
by Zilog in 1981. The EMSCC is a full-duplex data  
communications controller capable of supporting a  
wide range of popular protocols. The Z85233  
EMSCC is a single channel version (Channel A) of  
Zilog's Z85230 ESCC. Based on Zilog's unique  
Superintegration™ Technology, the EMSCC is  
compatible with designs using Zilog's SCC and  
ESCC to receive and transmit data. It has many  
improvements that significantly reduce CPU over-  
head. The addition of a 4-byte transmit FIFO and  
an 8-byte receive FIFO significantly reduces the  
overhead required to provide data to, and get data-  
from, the transmitter and receiver.  
–
–
Receive FIFO Automatically Unlocked for  
Special Receive Interrupts when Using the  
SDLC Status FIFO.  
Back-to-Back Frame Transmission Simpli-  
fied  
•
•
Easier Interface to Popular CPUs  
Fast Speeds:  
–
10.0 MHz for Data Rates up to 2.5 Mbit/  
Sec.  
–
16.384 MHz for Data Rates up to 4.096  
Mbit/Sec. -20.0 MHz for Data Rates up to  
5.0 Mbit/Sec.  
•
•
Improved SDLC Frame Status FIFO  
Low Power CMOS  
The EMSCC also has many features that improve  
packet handling in SDLC mode. The EMSCC will  
Copyright ©2008 by Zilog®, Inc. All rights reserved.  
www.zilog.com  
1234

中文翻译

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Z8523316VSG 替代型号

型号 品牌 替代类型 描述 数据表
Z8523316VSC ZILOG

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