Z5380

更新时间： 2024-01-01 04:05:37

品牌	Logo	应用领域
ZILOG		计算机
页数	文件大小	规格书
37页	242K
描述
SMALL COMPUTER SYSTEM INTERFACE (SCSI)

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中文翻译

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技术参数
数据手册

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Z5380 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	44
Reach Compliance Code：	unknown	风险等级：	5.84
最大数据传输速率：	0.1875 MBps	JESD-30 代码：	S-PQCC-J44
长度：	16.5862 mm	端子数量：	44
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	座面最大高度：	4.57 mm
表面贴装：	YES	技术：	CMOS
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	16.5862 mm
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, SCSI	Base Number Matches：	1

Z5380 数据手册

ILOG

Z5380 SCSI

Table 1. Register Summary

Address

Address: 0

(Read Only)

D7 D6 D5 D4 D3 D2 D1 D0

A2 A1 A0 R/W

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

R/W

Current SCSI Data

Output Data

Initiator Command

Mode

R/W

Target Command

Current SCSI Bus Status

Select Enable

Bus and Status

Start DMA Send

Input Data

Start DMA Target Receive

Reset Parity/Interrupt

Start DMA Initiator Receive

Figure 4. Current SCSI Data Register

Address: 0

(Write Only)

D7 D6 D5 D4 D3 D2 D1 D0

Data Registers

/DB0

/DB1

/DB2

/DB3

/DB4

/DB5

/DB6

/DB7

The data registers are used to transfer SCSI commands,

data, status, and message bytes between the micropro-

cessor Data Bus and the SCSI Bus. The Z5380 does not

interpret any information that passes through the data

registers. The data registers consist of the transparent

CurrentSCSIDataRegister, theOutputDataRegister, and

the Input Data Register.

Current SCSI Data Register. Address 0 (Read Only). The

Current SCSI Data Register (Figure 4) is a read-only

registerwhichallowsthemicroprocessortoreadtheactive

SCSI Data Bus. This is accomplished by activating /CS

withanaddressonA2-A0of000andissuingan/IORpulse.

If parity checking is enabled, the SCSI Bus parity is

checked at the beginning of the read cycle. This register

is used during a programmed I/O data read or during

Arbitration to check for higher priority arbitrating devices.

Parity is not guaranteed valid during Arbitration.

Figure 5. Output Data Register

Initiator Command Register. Address 1 (Read/Write).

The Initiator Command Register (Figures 6 and 7) are read

and write registers which assert certain SCSI Bus signals,

monitors those signals, and monitors the progress of bus

arbitration. Many of these bits are significant only when

being used as an Initiator; however, most can be used

during Target role operation.

OutputDataRegister.Address0(WriteOnly).TheOutput

Data Register (Figure 5) is a write-only register that is used

to send data to the SCSI Bus. This is accomplished by

either using a normal CPU write, or under DMA control, by

using /IOW and /DACK. This register also asserts the

proper ID bits on the SCSI Bus during the Arbitration and

Selection phases.

PS97SCC0100

PS009101-0201

1 2 3 456 7 8...37

中文翻译

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与Z5380相关器件

型号	品牌	获取价格	描述	数据表
Z538001PEC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z538001PSC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z538001VEC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z538001VSC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z5380P	ETC	获取价格	Interface IC
Z5380PSC	ZILOG	获取价格	SCSI Bus Controller, CMOS, PDIP40, PLASTIC, DIP-40
Z5380PSCXXXX	ZILOG	获取价格	SCSI Bus Controller, CMOS, PDIP40, PLASTIC, DIP-40
Z5380V	ETC	获取价格	Interface IC
Z5380VSC	ZILOG	获取价格	SCSI Bus Controller, CMOS, PQCC44, PLASTIC, LCC-44
Z5380VSCXXXX	ZILOG	获取价格	暂无描述

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