Z5380

更新时间： 2024-01-13 07:08:49

品牌	Logo	应用领域
ZILOG		计算机
页数	文件大小	规格书
37页	242K
描述
SMALL COMPUTER SYSTEM INTERFACE (SCSI)

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技术参数
数据手册

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Z5380 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	44
Reach Compliance Code：	unknown	风险等级：	5.84
最大数据传输速率：	0.1875 MBps	JESD-30 代码：	S-PQCC-J44
长度：	16.5862 mm	端子数量：	44
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装形状：	SQUARE	封装形式：	CHIP CARRIER
认证状态：	Not Qualified	座面最大高度：	4.57 mm
表面贴装：	YES	技术：	CMOS
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	16.5862 mm
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, SCSI	Base Number Matches：	1

Z5380 数据手册

ILOG

Z5380 SCSI

PIN DESCRIPTION (Continued)

IRQ Interrupt Request (Output, Active High). IRQ alerts a

microprocessor of an error condition or an event comple-

tion.

/DB7-/DB0, /DBP Data Bus Bits, Data Bus Parity Bit (Bi-

directional, Open-drain). These eight data bits (/DB7-/

DB0), plus a parity bit (/DBP) form the data bus. /DB7 is the

most significant bit (MSB) and has the highest priority

during the Arbitration phase. Data parity is odd. Parity is

always generated and optionally checked. Parity is not

valid during Arbitration.

READY Ready (Output, Active High). Ready is used to

control the speed of Block Mode DMA transfers. This

signal goes active to indicate the chip is ready to send/

receive data and remains Low after a transfer until the last

byte is sent or until the DMA Mode bit is reset.

I//O Input/Output (Bi-directional, Open-drain). I/O is a

signal driven by a Target which controls the direction of

datamovementontheSCSIbus.Trueindicatesinputtothe

Initiator. This signal is also used to distinguish between

Selection and Reselection phases.

/RESET Reset (Input, Active Low). /RESET clears all reg-

isters. It has no effect upon the SCSI /RST signal.

SCSI Bus

/MSG Message (Bi-directional, Open-drain, Active Low).

This signal is driven by the Target during the Message

phase. This signal is received by the Initiator.

The following signals are all bi-directional, active Low,

open-drain, with 48 mA sink capability. All pins interface

directly with the SCSI bus.

/REQ Request (Bi-directional, Open-drain, Active Low).

Driven by the Target and received by the Initiator, this

signal indicates a request for a /REQ//ACK data-transfer

handshake.

/ACK Acknowledge (Bi-directional, Open-drain, Active

Low). Driven by an Initiator, /ACK indicates an acknowl-

edgment for a /REQ//ACK data-transfer handshake. In the

Target role, /ACK is received as a response to the /REQ

signal.

/RST SCSI Bus Reset (Bi-directional, Open-drain, Active

Low). This signal indicates a SCSI bus Reset condition.

/ATN Attention (Bi-directional, Open-drain, Active Low).

Driven by an Initiator, received by the Target, /ATN indi-

cates an Attention condition.

/SEL Select (Bi-directional, Open-drain, Active Low). This

signal is used by an Initiator to select a Target, or by a

Target to reselect an Initiator.

/BSY Busy (Bi-directional, Open-drain, Active Low). This

signal indicates that the SCSI bus is being used and can

be driven by both the Initiator and the Target device.

C//D Control/Data (Bi-directional, Open-drain). Driven by

the Target and received by the Initiator, C//D indicates

whether Control or Data information is on the Data Bus.

True indicates Control.

FUNCTIONAL DESCRIPTION

The Z5380 Small Computer System Interface (SCSI) has a

set of eight registers that are controlled by the CPU. By

reading and writing the appropriate registers, the CPU

may initiate any SCSI Bus activity or may sample and

assert any signal on the SCSI Bus. This allows the user to

implementalloranyoftheSCSIprotocolinsoftware.These

registers are read (written) by activating /CS with an

address on A2-A0 and then issuing an /IOR (/IOW) pulse.

This section describes the operation of the internal regis-

ters (Table 1).

PS97SCC0100

PS009101-0201

1 2 345 6 7...37

中文翻译

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与Z5380相关器件

型号	品牌	获取价格	描述	数据表
Z538001PEC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z538001PSC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z538001VEC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z538001VSC	ZILOG	获取价格	SMALL COMPUTER SYSTEM INTERFACE (SCSI)
Z5380P	ETC	获取价格	Interface IC
Z5380PSC	ZILOG	获取价格	SCSI Bus Controller, CMOS, PDIP40, PLASTIC, DIP-40
Z5380PSCXXXX	ZILOG	获取价格	SCSI Bus Controller, CMOS, PDIP40, PLASTIC, DIP-40
Z5380V	ETC	获取价格	Interface IC
Z5380VSC	ZILOG	获取价格	SCSI Bus Controller, CMOS, PQCC44, PLASTIC, LCC-44
Z5380VSCXXXX	ZILOG	获取价格	暂无描述

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