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Z5380 PDF预览

Z5380

更新时间: 2024-01-24 17:06:41
品牌 Logo 应用领域
ZILOG 计算机
页数 文件大小 规格书
37页 242K
描述
SMALL COMPUTER SYSTEM INTERFACE (SCSI)

Z5380 技术参数

生命周期:Obsolete零件包装代码:LCC
包装说明:QCCJ,针数:44
Reach Compliance Code:unknown风险等级:5.84
最大数据传输速率:0.1875 MBpsJESD-30 代码:S-PQCC-J44
长度:16.5862 mm端子数量:44
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:CMOS
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD宽度:16.5862 mm
uPs/uCs/外围集成电路类型:BUS CONTROLLER, SCSIBase Number Matches:1

Z5380 数据手册

 浏览型号Z5380的Datasheet PDF文件第1页浏览型号Z5380的Datasheet PDF文件第2页浏览型号Z5380的Datasheet PDF文件第4页浏览型号Z5380的Datasheet PDF文件第5页浏览型号Z5380的Datasheet PDF文件第6页浏览型号Z5380的Datasheet PDF文件第7页 
Z
ILOG  
Z5380 SCSI  
D0  
/DB7  
/DB6  
/DB5  
/DB4  
/DB3  
/DB2  
/DB1  
/DB0  
/DBP  
GND  
/SEL  
/BSY  
/ACK  
/ATN  
/RST  
I//O  
1
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
D1  
2
D2  
3
D3  
6
5
4
3
2
1 44 43 42 41 40  
/DB3  
/DB2  
/DB1  
/DB0  
/DBP  
GND  
GND  
/SEL  
/BSY  
/ACK  
/ATN  
7
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
D6  
4
D4  
8
D7  
5
D5  
9
A2  
6
D6  
10  
11  
12  
13  
14  
15  
16  
17  
A1  
7
D7  
VDD  
N/C  
8
A2  
Z5380  
9
A1  
A0  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Z5380  
VDD  
A0  
/IOW  
/RESET  
/EOP  
/DACK  
/IOW  
/RESET  
/EOP  
/DACK  
READY  
/IOR  
IRQ  
DRQ  
/CS  
18 19 20 21 22 23 24 25 26 27 28  
C//D  
/MSG  
/REQ  
Figure 3b. 44-Pin PLCC Pin Configuration  
Figure 3a. 40-Pin DIP Pin Configuration  
PIN DESCRIPTION  
Microprocessor Bus  
D7-D0DataLines(Bi-directional,three-state,ActiveHigh).  
Bi-directional microprocessor data bus lines. D0 is the  
Least Significant Bit of the bus. Data bus lines carry data  
and commands to and from the SCSI.  
Figure 3 shows the pins and their respective functions for  
both the DIP and PLCC.  
A2-A0 Address Lines (Input). Address lines are used with  
/CS, /IOR, or /IOW to address all internal registers.  
/EOP End of Process (Input, Active Low). /EOP is used to  
terminate a DMA transfer. If asserted during a DMA cycle,  
the current byte will be transferred, but no additional bytes  
will be requested.  
/CS Chip Select (Input, Active Low). This signal, in con-  
junction with /IOR or /IOW, enables the internal register  
selected by A2-A0, to be read from or written to.  
/IOR I/O Read (Input, Active Low). /IOR is used in conjunc-  
tion with /CS and A2-A0 to read an internal register. It also  
selects the Input Data Register when used with /DACK.  
/DACK DMA Acknowledge (Input, Active Low). /DACK  
resetsDRQandselectsthedataregisterforinputoroutput  
datatransfers. /DACKisusedbyDMAcontrollerinsteadof  
/CS.  
/IOWI/OWrite(Input,ActiveLow)./IOWisusedinconjunc-  
tion with /CS and A2-A0 to write an internal register. It also  
selects the Output Data Register when used with /DACK.  
DRQ DMA Request (Output, Active High). DRQ indicates  
that the data register is ready to be read or written. DRQ is  
asserted only if DMA mode is set in the Command Regis-  
ter. DRQ is cleared by /DACK.  
3
PS97SCC0100  
PS009101-0201  

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