Z53C80

更新时间： 2024-01-12 02:31:45

品牌	Logo	应用领域
ZILOG		计算机
页数	文件大小	规格书
40页	450K
描述
SMALL COMPUTER SYSTEM INTERFACE (SCSI)

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技术参数
数据手册

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Z53C80 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	40
Reach Compliance Code：	unknown	风险等级：	5.83
最大数据传输速率：	0.375 MBps	驱动器接口标准：	X3.131
JESD-30 代码：	R-PDIP-T40	长度：	52.325 mm
端子数量：	40	封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	认证状态：	Not Qualified
座面最大高度：	4.96 mm	表面贴装：	NO
技术：	CMOS	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
宽度：	15.24 mm	uPs/uCs/外围集成电路类型：	BUS CONTROLLER, SCSI

Z53C80 数据手册

ILOG

Z53C80 SCSI

PRODUCT SPECIFICATION

Z53C80

SMALL COMPUTER

SYSTEM INTERFACE (SCSI)

FEATURES

■ Pin Compatible with the Industry Standard 5380

■ Asynchronous Interface (Supports 3 MB/s)

■ 44-Pin PLCC or 48-Pin DIP Package Styles

■ DMA or Programmed I/O Data Transfers

■ Arbitration Support

■ DirectSCSIBusInterfacewithOn-Board48mADrivers

■ Supports Target and Initiator Roles

■ Meets SCSI Protocol as Defined in ANSI X3.131-1986

Standard

■ Supports Normal or Block Mode DMA

■ Memory or I/O Mapped CPU Interface

■ Added “Glitch Eater” Enhancement to Minimize Bus

Reflection

GENERAL DESCRIPTION

The Z53C80 SCSI (Small Computer System Interface)

controller is designed to implement the SCSI protocol as

defined by the ANSI X3.131-1986 standard, and it is fully

compatible with the industry standard 5380. The device is

capable of operating both as a Target and as an Initiator.

Specialhigh-currentopen-drainoutputsenableittodirectly

interface to the SCSI bus. The Z53C80 has the necessary

interface hook-ups which allow the system CPU to

communicate with it as with any other peripheral device.

The CPU can read from, or write to, the SCSI registers

which are addressed as standard or memory-mapped

I/Os.

The added enhancement known as the “Glitch Eater” is

used to minimize effects of bus reflection on improperly

terminated SCSI bus applications. The high frequency

reflections that can occur on the SCSI bus are filtered out,

reducingthesensitivityoftheinputs,specifically/REQand

/ACKtobussignalreflections.Figure1showsaworstcase

input waveform (labeled A), along with the filtered input

(labeled B) and the output of a Schmitt trigger used to

provide the hysteresis required on SCSI inputs (labeled

C). This enhancement is a requirement for the device to

function properly in a Apple Macintosh^®environment.

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.,

B//W (WORD is active Low); /B/W (BYTE is active Low, only).

The Z53C80 increases the system performance by

minimizing the CPU intervention in DMA operations which

the SCSI controls. The CPU is interrupted by the SCSI

when it detects a bus condition that requires attention. It

also supports arbitration and reselection. The Z53C80 has

theproperhandshakesignalstosupportnormalandblock

modeDMAoperationswithmostDMAcontrollersavailable.

Power connections follow conventional descriptions below:

Connection

Circuit

Device

Power

Ground

V_CC

GND

V_DD

V_SS

^®Apple Macintosh is a registered trademark of Apple Computer, Inc.

PS97SCC0200

12 3 4 5 6 7...40

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