Datasheet > XRK32308_07

XRK32308_07

更新时间： 2024-11-01 03:13:51

品牌	Logo	应用领域
艾科嘉 - EXAR		/
页数	文件大小	规格书
16页	374K
描述
3.3V ZERO DELAY BUFFER

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XRK32308_07 数据手册

PRELIMINARY

XRK32308

3.3V ZERO DELAY BUFFER

FEBRUARY 2007

REV.P1.0.3

The XRK32308–1H is the high-drive version of the –

1. Rise and fall times on this device are faster.

GENERAL DESCRIPTION

FUNCTIONAL DESCRIPTION

The XRK32308–2 allows the user to obtain 1X, and

XRK32308 is a 3.3V Zero Delay Buffer designed to 2X or X/2 depending on which Bank sources the FB

distribute high-speed clocks in PC, workstation, signal.

datacom, telecom, and other high-performance

applications.

The XRK32308–3 allows the user to obtain 4X and

2X frequencies or 1X and 2X.

The part has an on-chip PLL which locks to an input

The XRK32308–4 enables the user to obtain 2X

clock presented on the REF pin. The PLL feedback is

clocks on all outputs.

required to be driven into the FB pin, and can be

The XRK32308–5H is a high-drive version with REF/

2 on both banks.

obtained from one of the outputs. The input-to-output

skew is guaranteed to be less than 350 ps, and

output-to-output skew is guaranteed to be less than

200 ps.

FEATURES

• Zero input-output propagation delay, adjustable by

XRK32308 has two banks of four outputs each.

These can be controlled by the Select inputs as

shown in Table 2, “Select Input Decoding,” on page 2.

If all output clocks are not required, Bank B can be

three-stated. The select inputs also allow the input

clock to be directly applied to the output for chip and

system testing purposes.

capacitive load on FB input

• Multiple configurations, see “Available XRK32308

Configurations” table

• Multiple low-skew outputs

• Two banks of four outputs, three-stateable by two

select inputs

Multiple XRK32308 devices can accept the same

input clock and distribute it in a system. In this case,

the skew between the outputs of two devices is

guaranteed to be less than 700 ps.

• 10-MHz to 120-MHz operating range

• 75ps typical cycle-to-cycle jitter (15pF, 66MHz)

• Space-saving 16-pin 150-mil SOIC package, 16-pin

TSSOP or 16-pin QFN

XRK32308 devices are available in five different

configurations, as shown in Table 3, “Available

XRK32308 Configurations,” on page 3.

• 3.3V operation

• Industrial and commercial temperature available

The XRK32308–1 is the base part, where the output

frequencies equal the reference if there is no counter

in the feedback path.

FIGURE 1. BLOCK DIAGRAM AND PIN CONFIGURATION OF THE XRK32308

QA0 REF FB QA3

REF

QA0

QA1

V_DD

PLL

MUX

REF

QA0

QA1

QA2

QA3

QA2

V_DD

GND

QB3

QB2

QA1

VDD

GND

QB0

QA2

VDD

GND

QB3

Extra Divider (-3, -4)

Extra Divider (-5H)

GND

QB0

QB1

Select Input

Decoding

QB0

QB1

QB2

QB3

QB1 S2 S1 QB2

Extra Divider (-2, -3)

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

12 3 4 5 6 7...16

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与XRK32308_07相关器件

型号	品牌	获取价格	描述	数据表
XRK32308-1	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32308-1H	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32308-2	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32308-3	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32308-4	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32308-5H	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32308CD-1	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32308CD-1H	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32308CD-2	EXAR	获取价格	3.3V ZERO DELAY BUFFER
XRK32308CD-3	EXAR	获取价格	3.3V ZERO DELAY BUFFER

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