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XR16C854CJTR-F PDF预览

XR16C854CJTR-F

更新时间: 2024-09-17 20:05:39
品牌 Logo 应用领域
艾科嘉 - EXAR 外围集成电路
页数 文件大小 规格书
53页 585K
描述
Serial I/O Controller, CMOS

XR16C854CJTR-F 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:,
Reach Compliance Code:unknownHTS代码:8542.31.00.01
风险等级:5.75JESD-609代码:e3
湿度敏感等级:3峰值回流温度(摄氏度):260
技术:CMOS端子面层:MATTE TIN
处于峰值回流温度下的最长时间:40uPs/uCs/外围集成电路类型:SERIAL IO/COMMUNICATION CONTROLLER, SERIAL
Base Number Matches:1

XR16C854CJTR-F 数据手册

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XR16C854/854D  
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO  
APRIL 2013  
REV. 3.1.0  
FEATURES  
GENERAL DESCRIPTION  
Added feature in devices with top mark date code of  
"F2 YYWW" and newer:  
The XR16C854/854D1 (854) is an enhanced quad  
Universal Asynchronous Receiver and Transmitter  
(UART) each with 128 bytes of transmit and receive  
FIFOs, transmit and receive FIFO counters and  
trigger levels, automatic hardware and software flow  
control, and data rates of up to 2 Mbps.  
5 volt tolerant inputs  
2.97 to 5.5 Volt Operation  
Pin-to-pin compatible with the industry standard  
ST16C554 and ST16C654 and TI’s TL16C554N  
and TL16C754BFN  
Each UART has a set of registers that provide the  
user with operating status and control, receiver error  
indications, and modem serial interface controls.  
System interrupts may be tailored to meet design  
requirements. An internal loopback capability allows  
onboard diagnostics.  
Intel or Motorola Data Bus Interface select  
Four independent UART channels  
Register Set Compatible to 16C550  
Data rates of up to 2 Mbps  
Transmit and Receive FIFOs of 128 bytes  
Programmable TX and RX FIFO Trigger Levels  
Transmit and Receive FIFO Level Counters  
Automatic Hardware (RTS/CTS) Flow Control  
Selectable Auto RTS Flow Control Hysteresis  
Automatic Software (Xon/Xoff) Flow Control  
Wireless Infrared (IrDA 1.0) Encoder/Decoder  
The 854 is available in 64-pin LQFP, 68-pin PLCC  
and 100-pin QFP packages. The 64-pin package  
only offers the 16 mode interface, but the 68 and 100  
pin packages offer an additional 68 mode interface  
which allows easy integration with Motorola  
processors.  
The XR16C854CV (64 pin) offers three state interrupt  
outputs while the XR16C854DV provides continuous  
interrupt outputs. The 100 pin package provides  
additional FIFO status outputs (TXRDY# and  
RXRDY# A-D), separate infrared transmit data  
outputs (IRTX A-D) and channel C external clock  
input (CHCCLK). The XR16C854/854D is compatible  
with the industry standard ST16C554/554D and  
ST16C654/654D.  
Sleep Mode (200 uA typical)  
Crystal oscillator or external clock input  
APPLICATIONS  
Portable Appliances  
Telecommunication Network Routers  
Ethernet Network Routers  
Cellular Data Devices  
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787.  
Factory Automation and Process Control  
FIGURE 1. XR16C854 BLOCK DIAGRAM  
2.97V to 5.5V VCC  
GND  
A2:A0  
D7:D0  
UART Channel A  
128 Byte TX FIFO  
IOR#  
IOW#  
UART  
TXA, RXA, IRTXA, DTRA#,  
DSRA#, RTSA#, CTSA#,  
CDA#, RIA#, OP2A#  
Regs  
IR  
ENDEC  
TX & RX  
CSA#  
CSB#  
CSC#  
CSD#  
BRG  
128 Byte RX FIFO  
TXB, RXB, IRTXB, DTRB#,  
DSRB#, RTSB#, CTSB#,  
CDB#, RIB#, OP2B#  
UART Channel B  
(same as Channel A)  
INTA  
INTB  
INTC  
Data Bus  
Interface  
TXC, RXC, IRTXC, DTRC#,  
DSRC#, RTSC#, CTSC#,  
CDC#, RIC#, OP2C#  
UART Channel C  
(same as Channel A)  
INTD  
CHCCLK  
TXRDY# A-D  
RXRDY# A-D  
TXD, RXD, IRTXD, DTRD#,  
DSRD#, RTSD#, CTSD#,  
CDD#, RID#, OP2D#  
UART Channel D  
(same as Channel A)  
Reset  
16/68#  
INTSEL  
XTAL1  
XTAL2  
Crystal Osc/Buffer  
854 BLK  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

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