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XR16C864IQTR-F PDF预览

XR16C864IQTR-F

更新时间: 2024-11-07 13:16:11
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艾科嘉 - EXAR 先进先出芯片
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XR16C864IQTR-F 数据手册

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XR16C864  
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO  
APRIL 2004  
REV. 2.0.1  
FEATURES  
GENERAL DESCRIPTION  
Added feature in devices with top mark date code of  
"F2 YYWW" and newer:  
The XR16C8641 (864) is an enhanced quad  
Universal Asynchronous Receiver and Transmitter  
(UART) each with 128 bytes of transmit and receive  
FIFOs, transmit and receive FIFO counters and  
trigger levels, automatic hardware and software flow  
control, automatic RS-485 half-duplex direction  
control and data rates of up to 2 Mbps. Each UART  
has a set of registers that provide the user with  
operating status and control, receiver error  
indications, and modem serial interface controls.  
System interrupts may be tailored to meet design  
requirements. An internal loopback capability allows  
onboard diagnostics. The 864 is available in the 100-  
pin QFP package. The XR16C864 offers faster  
channel status access by providing separate outputs  
for TXRDY and RXRDY, offer separate Infrared TX  
outputs and a separate clock input for channel C  
(CHCCLK). The XR16C864 is compatible with the  
industry standard ST16C554/554D, ST16C654/654D  
and XR16C854/854D.  
5 volt tolerant inputs  
2.97 to 5.5 Volt Operation  
Pin-to-pin compatible with the industry standard  
ST16C554 and ST16C654 and TI’s TL16C554N  
and TL16C754BFN  
Intel or Motorola Data Bus Interface select  
Four independent UART channels  
Register Set Compatible to 16C550  
Data rates of up to 2 Mbps  
Transmit and Receive FIFOs of 128 bytes  
Programmable TX and RX FIFO Trigger Levels  
Transmit and Receive FIFO Level Counters  
Automatic Hardware (RTS/CTS) Flow Control  
Selectable Auto RTS Flow Control Hysteresis  
Automatic Software (Xon/Xoff) Flow Control  
Wireless Infrared (IrDA 1.0) Encoder/Decoder  
Sleep Mode (200 uA typical)  
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787.  
Crystal oscillator or external clock input  
APPLICATIONS  
Portable Appliances  
Telecommunication Network Routers  
Ethernet Network Routers  
Cellular Data Devices  
Factory Automation and Process Controls  
FIGURE 1. XR16C864 BLOCK DIAGRAM  
2.97V to 5.5V VCC  
5V tolerant inputs (except XTAL1)  
UART Channel A  
A2:A0  
D7:D0  
128 Byte TX FIFO  
IOR#  
IOW#  
TXA, RXA, IRTXA, DTRA#,  
DSRA#, RTSA#, CTSA#,  
CDA#, RIA#, OP2A#,  
OP1A#/RS-485  
UART  
Regs  
BRG  
IR  
ENDEC  
TX & RX  
CS# A-D  
Intel or  
INT A-D  
Motorola  
128 Byte RX FIFO  
TXRDY# A-D  
RXRDY# A-D  
Reset  
Data Bus  
Interface  
TXB, RXB, IRTXB, DTRB#,  
DSRB#, RTSB#, CTSB#,  
CDB#, RIB#, OP2B#,  
OP1B#/RS-485  
UART Channel B  
(same as Channel A)  
16/68#  
INTSEL  
CLKSEL  
CHCCLK  
TXC, RXC, IRTXC, DTRC#,  
DSRC#, RTSC#, CTSC#,  
CDC#, RIC#, OP2C#,  
OP1C#/RS-485  
UART Channel C  
(same as Channel A)  
TC  
AEN  
DACK A-D  
Direct  
Memory  
Access  
TXDRQ# A-D  
RXDRQ# A-D  
TXD, RXD, IRTXD, DTRD#,  
DSRD#, RTSD#, CTSD#,  
CDD#, RID#, OP2D#,  
OP1D#/RS-485  
UART Channel D  
(same as Channel A)  
XTAL1  
XTAL2  
BCLK A-D  
Crystal Osc/Buffer  
854 BLK  
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com  

XR16C864IQTR-F 替代型号

型号 品牌 替代类型 描述 数据表
XR16C864IQ-F EXAR

完全替代

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

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