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PRELIMINARY
XRT7234
E3 UNI FOR ATM
NOVEMBER ‘999
REV. P1.0.0
(ATMLayer Processor)
1.0 SYSTEM DESCRIPTION
Whenever an ATM switch needs to transmit and receive
ATM cells to and from the UNI, it will typically use some
sort of “ATM Layer” processing entity to accomplish this
processing of cell data. This “ATM Switch Processing”
entity will be referred as the “ATM Layer Processor”
throughout this data sheet. The ATM Layer processor
interfaces with the XR- T7234 E3 UNI via the “Utopia
Bus” and will write in ATM cell data (in an 8- bit or 16- bit
wide parallel format) into the Transmit Utopia Interface
block (of the UNI). Additionally, the ATM Layer processor
will also receive ATM cells (in this same 8- bit or 16- bit
wide parallel format) from the Receive Utopia Interface
block (within the UNI IC).
The XR- T7234 E3 UNI IC for ATM consists of the following
functional sections/ blocks.
• Transmit Section
– Transmit Utopia Interface Block
– Transmit Cell Processor Block
– Transmit E3 Framer Block
• Receive Section
– Receive Utopia Interface Block
– Receive Cell Processor Block
– Receive E3 Framer Block
Interfacing to the Local Microprocessor
• Microprocessor Interface Section
• Performance Monitor Section
• Test and Diagnostic Section
In contrast to the ATM Layer Processor, the “local”
microprocessor (m P) interfaces with the UNI via the Micro-
processor Interface. This local “housekeeping” micropro-
cessor will typically read and write “configuration
information” from or into the on- chip registers within the
UNI IC. Further, the local microprocessor will respond to
UNI- generated interrupts, read and write PMDL (Path
Maintenance Data Link) Messages and OAM cell data
into and from the UNI IC. Finally, the local microprocessor
will “monitor” the performance of the overall system by peri-
odically reading the contents of the “Performance Monitor”
registers.
• Line Interface Drive and Scan Section
Each of these functional sections (and the blocks, within
these sections) combine to make a single chip device
that is capable of transmitting and receiving ATM cell
data via a E3 Transport Medium.
1.1 SYSTEM LEVEL INTERFACING
OF THE XR- T7234 E3 UNI
Note: The local m should not be confused with the ATM
Layer processor. The terms “local m P” and “ATM Layer
Processor” will be used throughout this data sheet in
order to make the distinction between these two “enti-
ties”.
1.2
• The system designer, when using the XR- T7234 E3
UNI IC for ATM, must (at a minimum) interface this
chip to the following entities.
Interfacing the UNI to the E3 Line
• The ATM Switch (or ATM Layer Processor)
• A local (housekeeping) microprocessor
• The E3 line
The UNI can be interfaced to a E3 line that is operating
over a copper or optical medium. If the user intends to
interface the UNI to a copper E3 line, (e.g., over coaxial
cable), then he/ she must connect the dual rail inputs
(RxPOS and RxNEG) and the dual rail outputs (TxPOS
and TxNEG) to a E3 Line Interface Unit (LIU) IC, (which is
transformer- coupled to the E3 line) in order to reliably
transmit and receive this data over the copper medium.
An example of such an LIU are the XR- T7295E (E3 Line
Figures 1 and 2 presents two illustrations of the UNI being
interfaced to these three entities. A brief discussion on
how to interface the UNI to these entities follows.
Interfacing to the ATM Switch
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 u (510) 668- 7000 u (510) 668- 7010