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XQ2V3000-4BG575N PDF预览

XQ2V3000-4BG575N

更新时间： 2024-09-20 03:13:59
品牌 Logo 应用领域
赛灵思 - XILINX 军事
页数 文件大小 规格书
128页 2774K
描述
QPro Virtex-II 1.5V Military QML Platform FPGAs

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XQ2V3000-4BG575N 数据手册

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QPro Virtex-II 1.5V Military QML  
Platform FPGAs  
0
0
DS122 (v1.1) January 7, 2004  
Product Specification  
Summary of QPro™ Virtex™-II Features  
•
Industry First Military Grade Platform FPGA Solution  
-
-
Fourth generation segmented routing structure  
Predictable, fast routing delay, independent of  
fanout  
•
Certified to MIL-PRF-38535 (Qualified Manufacturer  
Listing)  
•
SelectIO™-Ultra Technology  
•
•
100% Factory Tested  
Guaranteed over the full military temperature range  
(–55°C to +125° C)  
Ceramic and Plastic Wire-Bond and Flip-Chip Grid  
Array Packages  
-
-
-
Up to 824 user I/Os  
19 single-ended and six differential standards  
Programmable sink current (2 mA to 24 mA) per  
I/O  
•
•
-
Digitally Controlled Impedance (DCI) I/O: on-chip  
termination resistors for single-ended I/O standards  
PCI compliant (32/33 MHz) at 3.3V  
Differential Signaling  
IP-Immersion Architecture  
-
-
-
Densities from 1M to 6M system gates  
300+ MHz internal clock speed (Advance Data)  
622+ Mb/s I/O (Advance Data)  
-
-
·
622 Mb/s Low-Voltage Differential Signaling I/O  
(LVDS) with current mode drivers  
Bus LVDS I/O  
Lightning Data Transport (LDT) I/O with current  
driver buffers  
•
•
SelectRAM™ Memory Hierarchy  
-
2.5 Mb of dual-port RAM in 18 Kbit block  
SelectRAM resources  
·
·
-
Up to 1 Mb of distributed SelectRAM resources  
·
Low-Voltage Positive Emitter-Coupled Logic  
(LVPECL) I/O  
High-Performance Interfaces to External Memory  
-
DRAM interfaces  
·
Built-in DDR input and output registers  
·
·
·
SDR/DDR SDRAM  
Network FCRAM  
Reduced Latency DRAM  
-
Proprietary high-performance SelectLink  
Technology  
·
·
·
High-bandwidth data path  
Double Data Rate (DDR) link  
Web-based HDL generation methodology  
-
-
SRAM interfaces  
·
SDR/DDR SRAM  
·
QDR SRAM  
•
•
Supported by Xilinx Foundation Series™ and Alliance  
Series™ Development Systems  
CAM interfaces  
•
•
Arithmetic Functions  
-
-
-
-
-
Integrated VHDL and Verilog design flows  
Compilation of 10M system gates designs  
Internet Team Design (ITD) tool  
Dedicated 18-bit x 18-bit multiplier blocks  
Fast look-ahead carry logic chains  
Flexible Logic Resources  
-
SRAM-Based In-System Configuration  
Up to 67,584 internal registers/latches with Clock  
Enable  
Up to 67,584 look-up tables (LUTs) or cascadable  
16-bit shift registers  
Wide multiplexers and wide-input function support  
Horizontal cascade chain and sum-of-products  
support  
-
-
Fast SelectMAP configuration  
Triple Data Encryption Standard (DES) security  
option (Bitstream Encryption)  
IEEE 1532 support  
Partial reconfiguration  
Unlimited reprogrammability  
Readback capability  
-
-
-
-
-
-
-
-
Internal 3-state busing  
•
•
0.15 µm 8-Layer Metal Process with 0.12 µm  
High-Speed Transistors  
1.5V (VCCINT) Core Power Supply, Dedicated 3.3V  
VCCAUX Auxiliary and VCCO I/O Power Supplies  
•
•
High-Performance Clock Management Circuitry  
-
Up to 12 DCM (Digital Clock Manager) modules  
·
·
·
Precise clock de-skew  
Flexible frequency synthesis  
High-resolution phase shifting  
•
IEEE 1149.1 Compatible Boundary-Scan Logic  
Support  
-
16 global clock multiplexer buffers  
Active Interconnect Technology  
© 2004 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS122 (v1.1) January 7, 2004  
www.xilinx.com  
1
Product Specification  
1-800-255-7778  
1234567...128

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