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XPC7451RX667LG PDF预览

XPC7451RX667LG

更新时间: 2024-02-04 21:43:15
品牌 Logo 应用领域
其他 - ETC 外围集成电路微处理器时钟
页数 文件大小 规格书
2页 41K
描述
Microprocessor

XPC7451RX667LG 技术参数

生命周期:Transferred零件包装代码:BGA
包装说明:BGA,针数:483
Reach Compliance Code:unknownECCN代码:3A991
HTS代码:8542.31.00.01风险等级:5.52
地址总线宽度:36位大小:32
边界扫描:YES最大时钟频率:133 MHz
外部数据总线宽度:64格式:FLOATING POINT
集成缓存:YESJESD-30 代码:S-CBGA-B483
长度:29 mm低功率模式:YES
端子数量:483封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:3.22 mm速度:667 MHz
最大供电电压:1.65 V最小供电电压:1.55 V
标称供电电压:1.6 V表面贴装:YES
技术:CMOS端子形式:BALL
端子节距:1.27 mm端子位置:BOTTOM
宽度:29 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR, RISC
Base Number Matches:1

XPC7451RX667LG 数据手册

 浏览型号XPC7451RX667LG的Datasheet PDF文件第2页 
Fact Sheet  
MPC7450/MPC7451  
HIGH PERFORMANCE  
HOST MICROPROCESSOR  
SUPERSCALAR MICROPROCESSOR  
The MPC7450/MPC7451 host processor is a high-  
performance, low-power, 32-bit implementation of the  
PowerPC RISC architecture with a full 128-bit  
MPC7450/MPC7451 microprocessors feature a high-frequency superscalar G4 core,  
capable of issuing four instructions per clock cycle (three instructions + branch) into 11  
independent execution units:  
implementation of Motorolas AltiVec™ technology. This  
microprocessor is ideal for leading-edge computing, em-  
bedded network control, and signal processing  
applications. The MPC7450/MPC7451 has a deep, seven-  
stage pipeline with 11 execution units. The L2 cache has  
been integrated onto the die for greater speed, and  
supports a large backside L3 cache with a 64-bit  
datapath. The MPC7450/MPC7451 offers increased  
address space and high-bandwidth MPX bus with  
minimized signal setup times and reduced idle cycles to  
increase bus bandwidth to a maximum speed of 133 MHz.  
MPC7450/MPC7451 processors offer single-cycle,  
throughput, double-precision, floating-point performance  
and full symmetric multi-processing (SMP) capabilities.  
Finally, the MPC7450/MPC7451 is software-compatible  
with existing MPC6xx, MPC7xx, and MPC74xx host  
processors and exploits the full potential of AltiVec  
technology.  
Four integer units (3 simple + 1 complex)  
Double-precision floating-point unit  
Four AltiVec units (simple, complex, floating, and permute)  
Load/store unit  
Branch processing unit  
CACHE AND MMU SUPPORT  
The MPC7450/MPC7451 microprocessor has separate 32 KB, physically addressed  
instruction and data caches. Both L1 caches feature cache way locking and are eight-way  
set associative. For greater speed, the L2 cache has been integrated on-chip with a 256-  
bit interface to L1 which operates at processor frequency. This L2 is 256 kB eight-way set  
MPC7450/MPC7451 BLOCK DIAGRAM  
32 KB  
Instruction  
Cache  
Sequencer Unit  
Instruction Fetch  
Branch Unit  
Completion  
Unit  
BHT/  
BTIC  
Dispatch Unit  
AltiVec Issue  
GPR Issue  
FPR Issue  
GPRs  
Rename  
Buffers  
FPRs  
Rename  
Buffers  
FPU  
LSU  
CFX SFXO SFX1 SFX2  
Interface  
to Memory  
Sub-System  
VRs  
Rename  
Buffers  
32 kB  
Data  
Cache  
AltiVec Engine  
Unified L2 Cache/Tag L3 Control  
System Interface Unit  
60x/MPX bus interface  

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