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XPC7455RX1000PCR PDF预览

XPC7455RX1000PCR

更新时间: 2023-01-15 00:00:00
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
82页 1586K
描述
RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA483, 29 X 29 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, FCBGA-483

XPC7455RX1000PCR 数据手册

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Advance Information  
MPC7455EC/D  
Rev. 2, 1/2003  
MPC7455  
RISC Microprocessor  
Hardware Specifications  
This document is primarily concerned with the MPC7455; however, unless otherwise noted,  
all information here also applies to the MPC7445. The MPC7455 and MPC7445 are reduced  
instruction set computing (RISC) microprocessors that implement the PowerPC instruction  
set architecture. This document describes pertinent electrical and physical characteristics of  
the MPC7455. For functional characteristics of the processor, refer to the MPC7450 RISC  
Microprocessor Family Users Manual.  
This document contains the following topics:  
Topic  
Page  
Section 1.1, “Overview”  
Section 1.2, “Features”  
1
2
Section 1.3, “Comparison with the MPC7400, MPC7410, MPC7450, MPC7451,  
and MPC7441”  
7
Section 1.4, “General Parameters”  
Section 1.5, “Electrical and Thermal Characteristics”  
Section 1.6, “Pin Assignments”  
10  
10  
33  
35  
41  
45  
58  
60  
Section 1.7, “Pinout Listings”  
Section 1.8, “Package Description”  
Section 1.9, “System Design Information”  
Section 1.10, “Document Revision History”  
Section 1.11, “Ordering Information”  
To locate any published updates for this document, refer to the website at  
http://www.motorola.com/semiconductors.  
1.1 Overview  
The MPC7455 is the third implementation of the fourth generation (G4) microprocessors from  
Motorola. The MPC7455 implements the full PowerPC 32-bit architecture and is targeted at  
networking and computing systems applications. The MPC7455 consists of a processor core,  
a 256-Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3  
cache through a dedicated high-bandwidth interface. The MPC7445 is identical to the  
MPC7455 except it does not support the L3 cache interface.  

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