Datasheet > XPC745BPX350LD

XPC745BPX350LD

更新时间： 2024-01-29 06:42:57

品牌	Logo	应用领域
其他 - ETC		微处理器
页数	文件大小	规格书
2页	37K
描述
Microprocessor

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技术参数
数据手册

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XPC745BPX350LD 技术参数

生命周期：	Transferred	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.8
Base Number Matches：	1

XPC745BPX350LD 数据手册

Fact Sheet

MPC755

AND MPC745

MICROPROCESSORS

SUPERSCALAR MICROPROCESSOR

MPC755 and MPC745 microprocessors are high-performance, low-power, 32-bit

implementations of the PowerPC architecture, specially enhanced for embedded

applications. MPC755 and MPC745 microprocessors differ only in that the MPC755

features an enhanced, dedicated L2 cache interface with on-chip L2 tags. The MPC755

is a drop-in replacement for the award-winning MPC750 microprocessor and is

footprint- and user software code-compatible with the MPC7400 microprocessor with

AltiVec™ technology. The MPC745 is a drop-in replacement for the MPC740

microprocessor and is also footprint- and user software code-compatible with Motorola

G2 microprocessors. MPC755/MPC745 microprocessors provide on-chip debug support

and are fully JTAG-compliant.

MPC755 and MPC745 microprocessors are superscalar,

capable of issuing three instructions per clock cycle (two

instructions + branch) into six independent execution units:

• Two integer units

• Load/store unit

• Double-precision floating-point unit

• System register unit

• Branch processing unit

MOTOROLA MPC755/MPC745 BLOCK DIAGRAM

Completion

Branch

Unit

Dispatch

Unit

Load/

Gen

Floating

FPU

Integer

Unit

Gen

Store

Unit

Point

Reg

File

Rename

Unit

File

D MMU

Data Cache

I MMU

Inst. Cache

Bus Interface Unit

L2 Tags

L2 Cache

32-bit Address 32-/64-bit Data

System Bus

Port (755 only)

FSRAM

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