Datasheet > XPC7450RX867QE

XPC7450RX867QE

更新时间： 2024-09-25 23:33:59

品牌	Logo	应用领域
其他 - ETC		微处理器
页数	文件大小	规格书
2页	41K
描述
Microprocessor

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XPC7450RX867QE 数据手册

Fact Sheet

MPC7450/MPC7451

HIGH PERFORMANCE

HOST MICROPROCESSOR

SUPERSCALAR MICROPROCESSOR

The MPC7450/MPC7451 host processor is a high-

performance, low-power, 32-bit implementation of the

PowerPC RISC architecture with a full 128-bit

MPC7450/MPC7451 microprocessors feature a high-frequency superscalar G4 core,

capable of issuing four instructions per clock cycle (three instructions + branch) into 11

independent execution units:

implementation of Motorola’s AltiVec™ technology. This

microprocessor is ideal for leading-edge computing, em-

bedded network control, and signal processing

applications. The MPC7450/MPC7451 has a deep, seven-

stage pipeline with 11 execution units. The L2 cache has

been integrated onto the die for greater speed, and

supports a large backside L3 cache with a 64-bit

datapath. The MPC7450/MPC7451 offers increased

address space and high-bandwidth MPX bus with

minimized signal setup times and reduced idle cycles to

increase bus bandwidth to a maximum speed of 133 MHz.

MPC7450/MPC7451 processors offer single-cycle,

throughput, double-precision, floating-point performance

and full symmetric multi-processing (SMP) capabilities.

Finally, the MPC7450/MPC7451 is software-compatible

with existing MPC6xx, MPC7xx, and MPC74xx host

processors and exploits the full potential of AltiVec

technology.

• Four integer units (3 simple + 1 complex)

• Double-precision floating-point unit

• Four AltiVec units (simple, complex, floating, and permute)

• Load/store unit

• Branch processing unit

CACHE AND MMU SUPPORT

The MPC7450/MPC7451 microprocessor has separate 32 KB, physically addressed

instruction and data caches. Both L1 caches feature cache way locking and are eight-way

set associative. For greater speed, the L2 cache has been integrated on-chip with a 256-

bit interface to L1 which operates at processor frequency. This L2 is 256 kB eight-way set

MPC7450/MPC7451 BLOCK DIAGRAM

32 KB

Instruction

Cache

Sequencer Unit

Instruction Fetch

Branch Unit

Completion

Unit

BHT/

BTIC

Dispatch Unit

AltiVec Issue

GPR Issue

FPR Issue

GPRs

Rename

Buffers

FPRs

Rename

Buffers

FPU

LSU

CFX SFXO SFX1 SFX2

Interface

to Memory

Sub-System

VRs

Rename

Buffers

32 kB

Data

Cache

AltiVec Engine

Unified L2 Cache/Tag L3 Control

System Interface Unit

60x/MPX bus interface

中文翻译

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与XPC7450RX867QE相关器件

型号	品牌	获取价格	描述	数据表
XPC7451RX600LG	ETC	获取价格	Microprocessor
XPC7451RX667LG	ETC	获取价格	Microprocessor
XPC7451RX700RE	NXP	获取价格	XPC7451RX700RE
XPC7451RX733PG	MOTOROLA	获取价格	32-BIT, 733MHz, RISC PROCESSOR, CBGA484, CERAMIC, BGA-484
XPC7451RX800RE	NXP	获取价格	XPC7451RX800RE
XPC7451RX800SG	MOTOROLA	获取价格	32-BIT, 800MHz, RISC PROCESSOR, CBGA484, CERAMIC, BGA-484
XPC7451RX867PG	MOTOROLA	获取价格	32-BIT, 867MHz, RISC PROCESSOR, CBGA484, CERAMIC, BGA-484
XPC7455RX1000PC	MOTOROLA	获取价格	32-BIT, 1000MHz, RISC PROCESSOR, CBGA483, 29 X 29 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAM
XPC7455RX1000PCR	MOTOROLA	获取价格	RISC Microprocessor, 32-Bit, 1000MHz, CMOS, CBGA483, 29 X 29 MM, 3.20 MM HEIGHT, 1.27 MM P
XPC7455RX600NC	MOTOROLA	获取价格	32-BIT, 600 MHz, RISC PROCESSOR, CBGA483, 29 X 29 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAM

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