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XCV1600E-7BGG560I

更新时间： 2024-09-10 14:45:43
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赛灵思 - XILINX 时钟栅可编程逻辑
页数 文件大小 规格书
54页 581K
描述
Field Programmable Gate Array, 7776 CLBs, 419904 Gates, 400MHz, 34992-Cell, CMOS, PBGA560, BGA-560

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XCV1600E-7BGG560I 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA, BGA560,33X33,50针数：560
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.82最大时钟频率：400 MHz
CLB-Max的组合延迟：0.42 nsJESD-30 代码：S-PBGA-B560
JESD-609代码：e1长度：42.5 mm
湿度敏感等级：3可配置逻辑块数量：7776
等效关口数量：419904输入次数：404
逻辑单元数量：34992输出次数：404
端子数量：560组织：7776 CLBS, 419904 GATES
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA560,33X33,50封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE峰值回流温度（摄氏度）：260
电源：1.2/3.6,1.8 V可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY
认证状态：Not Qualified座面最大高度：1.7 mm
子类别：Field Programmable Gate Arrays最大供电电压：1.89 V
最小供电电压：1.71 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
端子面层：Tin/Silver/Copper (Sn95.5Ag4.0Cu0.5)端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：42.5 mm
Base Number Matches：1

XCV1600E-7BGG560I 数据手册

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0
R
Virtex™-E 1.8 V  
Field Programmable Gate Arrays  
0
0
DS022-2 (v2.8) January 16, 2006  
Production Product Specification  
Architectural Description  
Virtex-E Array  
The Virtex-E user-programmable gate array, shown in  
Figure 1, comprises two major configurable elements: con-  
figurable logic blocks (CLBs) and input/output blocks (IOBs).  
Values stored in static memory cells control the configurable  
logic elements and interconnect resources. These values  
load into the memory cells on power-up, and can reload if  
necessary to change the function of the device.  
•
CLBs provide the functional elements for constructing  
logic  
Input/Output Block  
The Virtex-E IOB, Figure 2, features SelectI/O+ inputs and  
outputs that support a wide variety of I/O signalling stan-  
dards, see Table 1.  
•
IOBs provide the interface between the package pins  
and the CLBs  
CLBs interconnect through a general routing matrix (GRM).  
The GRM comprises an array of routing switches located at  
the intersections of horizontal and vertical routing channels.  
Each CLB nests into a VersaBlock™ that also provides local  
routing resources to connect the CLB to the GRM.  
Q
D
CE  
T
TCE  
Weak  
Keeper  
SR  
PAD  
DLLDLL  
DLLDLL  
O
Q
D
CE  
OCE  
OBUFT  
VersaRing  
SR  
I
IQ  
Programmable  
Delay  
Q
D
CE  
IBUF  
Vref  
SR  
SR  
CLK  
ICE  
ds022_02_091300  
Figure 2: Virtex-E Input/Output Block (IOB)  
The three IOB storage elements function either as  
edge-triggered D-type flip-flops or as level-sensitive latches.  
Each IOB has a clock signal (CLK) shared by the three  
flip-flops and independent clock enable signals for each  
flip-flop.  
VersaRing  
DLLDLL  
DLLDLL  
ds022_01_121099  
Figure 1: Virtex-E Architecture Overview  
The VersaRing™ I/O interface provides additional routing  
resources around the periphery of the device. This routing  
improves I/O routability and facilitates pin locking.  
The Virtex-E architecture also includes the following circuits  
that connect to the GRM.  
•
•
Dedicated block memories of 4096 bits each  
Clock DLLs for clock-distribution delay compensation  
and clock domain control  
•
3-State buffers (BUFTs) associated with each CLB that  
drive dedicated segmentable horizontal routing  
resources  
© 2000–2006 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS022-2 (v2.8) January 16, 2006  
Production Product Specification  
www.xilinx.com  
Module 2 of 4  
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