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XCF01SVOG20C0936 PDF预览

XCF01SVOG20C0936

更新时间： 2024-01-25 03:37:09
品牌 Logo 应用领域
赛灵思 - XILINX 光电二极管内存集成电路
页数 文件大小 规格书
42页 456K
描述
Configuration Memory, 1MX1, Serial, CMOS, PDSO20, LEAD FREE, PLASTIC, TSSOP-20

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XCF01SVOG20C0936 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：20
Reach Compliance Code：compliantECCN代码：3A991.B.1
HTS代码：8542.32.00.51风险等级：5.5
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：6.5024 mm内存密度：1048576 bit
内存集成电路类型：CONFIGURATION MEMORY内存宽度：1
湿度敏感等级：3功能数量：1
端子数量：20字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX1封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行：SERIAL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.19 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

XCF01SVOG20C0936 数据手册

 浏览型号XCF01SVOG20C0936的Datasheet PDF文件第1页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第3页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第4页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第5页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第6页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第7页 
R
Platform Flash In-System Programmable Configuration PROMS  
CLK CE  
OE/RESET  
TCK  
TMS  
TDI  
Data  
Control  
and  
JTAG  
CEO  
Serial  
Memory  
Interface  
Data  
DATA (D0)  
Serial Mode  
Address  
Interface  
TDO  
CF  
ds123_01_30603  
Figure 1: XCFxxS Platform Flash PROM Block Diagram  
FI  
CLK CE  
EN_EXT_SEL  
OE/RESET BUSY  
CLKOUT  
CEO  
OSC  
Control  
and  
JTAG  
Serial  
or  
Parallel  
Interface  
TCK  
TMS  
TDI  
Data  
Memory  
DATA (D0)  
(Serial/Parallel Mode)  
Address  
TDO  
Interface  
Data  
Decompressor  
D[1:7]  
(Parallel Mode)  
ds123_19_050604  
CF  
REV_SEL [1:0]  
Figure 2: XCFxxP Platform Flash PROM Block Diagram  
When the FPGA is in Master Serial mode, it generates a  
configuration clock that drives the PROM. With CF High, a  
short access time after CE and OE are enabled, data is  
available on the PROM DATA (D0) pin that is connected to  
the FPGA DIN pin. New data is available a short access  
time after each rising clock edge. The FPGA generates the  
appropriate number of clock pulses to complete the config-  
uration.  
CF High, after CE and OE are enabled, data is available on  
the PROMs DATA (D0-D7) pins. New data is available a  
short access time after each rising clock edge. The data is  
clocked into the FPGA on the following rising edge of the  
CCLK. A free-running oscillator can be used in the Slave  
Parallel /Slave SelecMAP mode.  
The XCFxxP version of the Platform Flash PROM provides  
additional advanced features. A built-in data decompressor  
supports utilizing compressed PROM files, and design revi-  
sioning allows multiple design revisions to be stored on a  
single PROM or stored across several PROMs. For design  
revisioning, external pins or internal control bits are used to  
select the active design revision.  
When the FPGA is in Slave Serial mode, the PROM and the  
FPGA are both clocked by an external clock source, or  
optionally, for the XCFxxP PROM only, the PROM can be  
used to drive the FPGA’s configuration clock.  
The XCFxxP version of the Platform Flash PROM also sup-  
ports Master SelectMAP and Slave SelectMAP (or Slave  
Parallel) FPGA configuration modes. When the FPGA is in  
Master SelectMAP mode, the FPGA generates a configura-  
tion clock that drives the PROM. When the FPGA is in Slave  
SelectMAP Mode, either an external oscillator generates  
the configuration clock that drives the PROM and the  
FPGA, or optionally, the XCFxxP PROM can be used to  
drive the FPGA’s configuration clock. With BUSY Low and  
Multiple Platform Flash PROM devices can be cascaded to  
support the larger configuration files required when target-  
ing larger FPGA devices or targeting multiple FPGAs daisy  
chained together. When utilizing the advanced features for  
the XCFxxP Platform Flash PROM, such as design revi-  
sioning, programming files which span cascaded PROM  
devices can only be created for cascaded chains containing  
only XCFxxP PROMs. If the advanced XCFxxP features are  
DS123 (v2.4) July 20, 2004  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
2
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