5秒后页面跳转
捷配首页

Datasheet > XCF01SVOG20C0936
XCF01SVOG20C0936 PDF预览

XCF01SVOG20C0936

更新时间： 2024-01-10 02:34:07
品牌 Logo 应用领域
赛灵思 - XILINX 光电二极管内存集成电路
页数 文件大小 规格书
42页 456K
描述
Configuration Memory, 1MX1, Serial, CMOS, PDSO20, LEAD FREE, PLASTIC, TSSOP-20

阅读下载

获取价格

XCF01SVOG20C0936 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：20
Reach Compliance Code：compliantECCN代码：3A991.B.1
HTS代码：8542.32.00.51风险等级：5.5
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：6.5024 mm内存密度：1048576 bit
内存集成电路类型：CONFIGURATION MEMORY内存宽度：1
湿度敏感等级：3功能数量：1
端子数量：20字数：1048576 words
字数代码：1000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：1MX1封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH并行/串行：SERIAL
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.19 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：4.4 mmBase Number Matches：1

XCF01SVOG20C0936 数据手册

 浏览型号XCF01SVOG20C0936的Datasheet PDF文件第3页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第4页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第5页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第7页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第8页浏览型号XCF01SVOG20C0936的Datasheet PDF文件第9页 
R
Platform Flash In-System Programmable Configuration PROMS  
Table 6: Platform Flash PROM Boundary Scan Instructions  
XCFxxS IR[7:0] XCFxxP IR[15:0]  
Boundary-Scan Command  
Required Instructions  
BYPASS  
(hex)  
(hex)  
Instruction Description  
Enables BYPASS  
FF  
01  
00  
FFFF  
0001  
0000  
Enables boundary-scan SAMPLE/PRELOAD operation  
Enables boundary-scan EXTEST operation  
SAMPLE/PRELOAD  
EXTEST  
Optional Instructions  
CLAMP  
Enables boundary-scan CLAMP operation  
FA  
FC  
00FA  
00FC  
Places all outputs in high-impedance state  
simultaneously  
HIGHZ  
Enables shifting out 32-bit IDCODE  
IDCODE  
FE  
FD  
00FE  
00FD  
Enables shifting out 32-bit USERCODE  
USERCODE  
PlatformFlashPROMSpecific  
Instructions  
Initiates FPGA configuration by pulsing CF pin Low  
once. (For the XCFxxP this command also resets the  
selected design revision based on either the external  
REV_SEL[1:0] pins or on the internal design revision  
selection bits.)(1)  
CONFIG  
EE  
00EE  
Notes:  
1. For more information see Initiating FPGA Configuration.  
IR[7:5]  
IR[4]  
IR[3]  
Security  
IR[2]  
IR[1:0]  
TDI →  
→ TDO  
Reserved  
ISC Status  
0
0 1  
Figure 4: XCFxxS Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence  
IR[15:9]  
IR[8:7]  
IR[6:5]  
ER/PROG ER/PROG  
Error Status  
IR[4]  
IR[3]  
IR[2]  
IR[1:0]  
TDI →  
→ TDO  
Reserved  
ISC Error  
ISC Status  
DONE  
0 1  
Figure 5: XCFxxP Instruction Capture Values Loaded into IR as part of an Instruction Scan Sequence  
Boundary Scan Register  
The boundary-scan register is used to control and observe  
the state of the device pins during the EXTEST, SAM-  
PLE/PRELOAD, and CLAMP instructions. Each output pin  
on the Platform Flash PROM has two register stages which  
contribute to the boundary-scan register, while each input  
pin has only one register stage. The bidirectional pins have  
a total of three register stages which contribute to the  
boundary-scan register. For each output pin, the register  
stage nearest to TDI controls and observes the output state,  
and the second stage closest to TDO controls and observes  
the High-Z enable state of the output pin. For each input pin,  
a single register stage controls and observes the input state  
of the pin. The bidirectional pin combines the three bits, the  
input stage bit is first, followed by the output stage bit and  
finally the output enable stage bit. The output enable stage  
bit is closest to TDO.  
See the XCFxxS/XCFxxP Pin Names and Descriptions  
Tables in the Pinouts and Pin Descriptions section for the  
boundary-scan bit order for all connected device pins, or  
see the appropriate BSDL file for the complete bound-  
ary-scan bit order description under the "attribute  
BOUNDARY_REGISTER" section in the BSDL file. The bit  
assigned to boundary-scan cell "0" is the LSB in the bound-  
ary-scan register, and is the register bit closest to TDO.  
DS123 (v2.4) July 20, 2004  
Preliminary Product Specification  
www.xilinx.com  
1-800-255-7778  
6
1...3456789...42

下载PDF

与XCF01SVOG20C0936相关器件

型号 品牌 描述 获取价格 数据表
XCF01SVOG48 XILINX Platform Flash In-System Programmable Configuration PROMS

获取价格
XCF01SX XILINX Platform Flash In-System Programmable Configuration PROMS

获取价格
XCF02S XILINX Platform Flash In-System Programmable Configuration PROMS

获取价格
XCF02SF48 XILINX Platform Flash In-System Programmable Configuration PROMS

获取价格
XCF02SFG48 XILINX Platform Flash In-System Programmable Configuration PROMS

获取价格
XCF02SV XILINX Platform Flash In-System Programmable Configuration PROMS

获取价格

与XCF01SVOG20C0936相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证