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XC95144 In-System Programmable
CPLD
1
1*
December 4, 1998 (Version 4.0)
Product Specification
Operating current for each design can be approximated for
specific operating conditions using the following equation:
Features
•
•
7.5 ns pin-to-pin logic delays on all pins
to 111 MHz
I
(mA) =
CC
MC
f
CNT
(1.7) + MC (0.9) + MC (0.006 mA/MHz) f
•
•
•
144 macrocells with 3,200 usable gates
Up to 133 user I/O pins
5 V in-system programmable
HP
Where:
MC
LP
= Macrocells in high-performance mode
HP
-
-
Endurance of 10,000 program/erase cycles
Program/erase over full commercial voltage and
temperature range
MC = Macrocells in low-power mode
LP
MC = Total number of macrocells used
f = Clock frequency (MHz)
•
•
Enhanced pin-locking architecture
Flexible 36V18 Function Block
-
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables, set
and reset signals
Figure 1 shows a typical calculation for the XC95144
device.
-
•
•
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
600
(480)
•
•
•
•
•
•
•
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs
400
High Performance
Low Power
(320)
(300)
3.3 V or 5 V I/O capability
200
Advanced CMOS 5V FastFLASH technology
Supports parallel programming of more than one
XC9500 concurrently
(160)
•
Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
0
50
100
Clock Frequency (MHz)
X5898B
Description
The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architec-
ture overview.
Figure 1: Typical Icc vs. Frequency for XC95144
Power Management
Power dissipation can be reduced in the XC95144 by con-
figuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
December 4, 1998 (Version 4.0)
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