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XC95144XL-10TQG144C PDF预览

XC95144XL-10TQG144C

更新时间： 2024-09-21 15:58:23
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
12页 190K
描述
Flash PLD, 10ns, 144-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144

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XC95144XL-10TQG144C 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：QFP
包装说明：LFQFP, QFP144,.87SQ,20针数：144
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：0.93Is Samacsys：N
其他特性：YES系统内可编程：YES
JESD-30 代码：S-PQFP-G144JESD-609代码：e3
JTAG BST：YES长度：20 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：117宏单元数：144
端子数量：144最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 117 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP144,.87SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：2.5/3.3,3.3 V
可编程逻辑类型：FLASH PLD传播延迟：10 ns
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Programmable Logic Devices最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：20 mmBase Number Matches：1

XC95144XL-10TQG144C 数据手册

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0
R
XC95144XL High Performance  
CPLD  
0
0
DS056 (v2.0) April 3, 2007  
Product Specification  
54V18 Function Blocks, providing 3,200 usable gates with  
propagation delays of 5 ns. See Figure 2 for overview.  
Features  
•
•
•
•
5 ns pin-to-pin logic delays  
Power Estimation  
System frequency up to 178 MHz  
144 macrocells with 3,200 usable gates  
Available in small footprint packages  
Power dissipation in CPLDs can vary substantially depend-  
ing on the system frequency, design application and output  
loading. To help reduce power dissipation, each macrocell  
in a XC9500XL device may be configured for low-power  
mode (from the default high-performance mode). In addi-  
tion, unused product-terms and macrocells are automati-  
cally deactivated by the software to further conserve power.  
-
-
-
-
100-pin TQFP (81 user I/O pins)  
144-pin TQFP (117 user I/O pins)  
144-CSP (117 user I/O pins)  
Pb-free available for all packages  
•
•
Optimized for high-performance 3.3V systems  
-
-
Low power operation  
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V  
signals  
For a general estimate of ICC, the following equation may be  
used:  
I
CC(mA) = MCHS(0.175*PTHS + 0.345) + MCLP(0.052*PTLP  
+ 0.272) + 0.04 * MCTOG(MCHS +MCLP)* f  
-
-
3.3V or 2.5V output capability  
Advanced 0.35 micron feature size CMOS  
Fast FLASH™ technology  
where:  
MCHS = # macrocells in high-speed configuration  
PTHS = average number of high-speed product terms  
per macrocell  
MCLP = # macrocells in low power configuration  
PTLP = average number of low power product terms per  
macrocell  
f = maximum clock frequency  
MCTOG = average % of flip-flops toggling per clock  
(~12%)  
Advanced system features  
-
-
In-system programmable  
Superior pin-locking and routability with  
Fast CONNECT™ II switch matrix  
Extra wide 54-input Function Blocks  
Up to 90 product-terms per macrocell with  
individual product-term allocation  
Local clock inversion with three global and one  
product-term clocks  
Individual output enable per output pin with local  
inversion  
Input hysteresis on all user and boundary-scan pin  
inputs  
-
-
-
-
-
This calculation was derived from laboratory measurements  
of an XC9500XL part filled with 16-bit counters and allowing  
a single output (the LSB) to be enabled. The actual ICC  
value varies with the design application and should be veri-  
fied during normal system operation. Figure 1 shows the  
above estimation in a graphical form. For a more detailed  
discussion of power consumption in this device, see Xilinx  
-
-
Bus-hold circuitry on all user pin inputs  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
•
•
•
•
Fast concurrent programming  
Slew rate control on individual outputs  
Enhanced data security features  
Excellent quality and reliability  
-
Endurance exceeding 10,000 program/erase  
cycles  
-
-
20 year data retention  
ESD protection exceeding 2,000V  
•
Pin-compatible with 5V-core XC95144 device in the  
100-pin TQFP package  
WARNING: Programming temperature range of  
TA = 0° C to +70° C  
Description  
The XC95144XL is a 3.3V CPLD targeted for high-perfor-  
mance, low-voltage applications in leading-edge communi-  
cations and computing systems. It is comprised of eight  
© 1998-2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS056 (v2.0) April 3, 2007  
www.xilinx.com  
1
Product Specification  
1234567...12

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XC95144XL-10TQG144C 替代型号

型号 品牌 替代类型 描述 数据表
XC95144XL-7TQG144I XILINX

完全替代

 Flash PLD, 7.5ns, 144-Cell, CMOS, PQFP144, LEAD FREE, TQFP-144
XC95144XL-7TQ144I XILINX

完全替代

 XC95144XL High Performance CPLD

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