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XC95144XV-4CS144I

更新时间： 2024-01-25 13:03:51
品牌 Logo 应用领域
赛灵思 - XILINX 可编程逻辑器件输入元件
页数 文件大小 规格书
9页 82K
描述
High-Performance CPLD

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中文翻译

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XC95144XV-4CS144I 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：PLASTIC, CSP-144
针数：144Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.69
Is Samacsys：NJESD-30 代码：S-PBGA-B144
JESD-609代码：e0长度：12 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：117端子数量：144
最高工作温度：85 °C最低工作温度：-40 °C
组织：0 DEDICATED INPUTS, 117 I/O输出函数：REGISTERED
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：SQUARE封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：240可编程逻辑类型：FLASH PLD
传播延迟：4 ns认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压：2.6 V
最小供电电压：2.4 V标称供电电压：2.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：12 mm
Base Number Matches：1

XC95144XV-4CS144I 数据手册

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0
R
XC95144XV High-Performance  
CPLD  
0
1
DS051 (v2.2) August 27, 2001  
Advance Product Specification  
Features  
Power Estimation  
•
144 macrocells with 3,200 usable gates  
Power dissipation in CPLDs can vary substantially depend-  
ing on the system frequency, design application and output  
loading. To help reduce power dissipation, each macrocell  
in a XC9500XV device may be configured for low-power  
mode (from the default high-performance mode). In addi-  
tion, unused product-terms and macrocells are automati-  
cally deactivated by the software to further conserve power.  
•
Available in small footprint packages  
-
-
-
100-pin TQFP (81 user I/O pins)  
144-pin TQFP (117 user I/O pins)  
144-pin CSP (117 user I/O pins)  
•
•
Optimized for high-performance 2.5V systems  
-
-
Low power operation  
Multi-voltage operation  
For a general estimate of I , the following equation may be  
CC  
used:  
Advanced system features  
I
(mA) =  
CC  
-
-
-
In-system programmable  
Two separate output banks  
MC (0.36) + MC (0.23) + MC(0.005 mA/MHz) f  
HP  
LP  
Superior pin-locking and routability with  
FastCONNECT II™ switch matrix  
Extra wide 54-input Function Blocks  
Up to 90 product-terms per macrocell with  
individual product-term allocation  
Where:  
MC = Macrocells in high-performance (default) mode  
HP  
-
-
MC = Macrocells in low-power mode  
LP  
MC = Total number of macrocells used  
f = Clock frequency (MHz)  
-
Local clock inversion with three global and one  
product-term clocks  
This calculation is based on typical operating conditions  
using a pattern of 16-bit up/down counters in each Function  
-
-
Individual output enable per output pin  
Input hysteresis on all user and boundary-scan pin  
inputs  
Block with no output loading. The actual I  
value varies  
CC  
with the design application and should be verified during  
normal system operation.  
-
-
Bus-hold ciruitry on all user pin inputs  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Figure 1 shows the above estimation in a graphical form.  
•
•
•
•
Fast concurrent programming  
Slew rate control on individual outputs  
Enhanced data security features  
Excellent quality and reliability  
200  
200 MHz  
150  
-
Endurance exceeding 10,000 program/erase  
cycles  
120 MHz  
-
-
20 year data retention  
ESD protection exceeding 2,000V  
100  
Description  
50  
The XC95144XV is a 2.5V CPLD targeted for high-perfor-  
mance, low-voltage applications in leading-edge communi-  
cations and computing systems. It is comprised of eight  
54V18 Function Blocks, providing 3,200 usable gates with  
propagation delays of 4 ns.  
0
120  
Clock Frequency (MHz)  
200  
40  
80  
160  
DS051_01_012501  
Figure 1: Typical I vs. Frequency for XC95144XV  
CC  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS051 (v2.2) August 27, 2001  
www.xilinx.com  
1
Advance Product Specification  
1-800-255-7778  
1234567...9

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