5秒后页面跳转
捷配首页

Datasheet > XC95144XV-4CSG144I
XC95144XV-4CSG144I PDF预览

XC95144XV-4CSG144I

更新时间： 2024-01-05 14:16:15
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
9页 80K
描述
Flash PLD, 4ns, PBGA144, PLASTIC, CSP-144

阅读下载

中文翻译

获取价格

XC95144XV-4CSG144I 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：PLASTIC, CSP-144
针数：144Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.65
JESD-30 代码：S-PBGA-B144JESD-609代码：e1
长度：12 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：117
端子数量：144最高工作温度：85 °C
最低工作温度：-40 °C组织：0 DEDICATED INPUTS, 117 I/O
输出函数：REGISTERED封装主体材料：PLASTIC/EPOXY
封装代码：TFBGA封装形状：SQUARE
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：260
可编程逻辑类型：FLASH PLD传播延迟：4 ns
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：2.6 V最小供电电压：2.4 V
标称供电电压：2.5 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：TIN SILVER COPPER
端子形式：BALL端子节距：0.8 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：30
宽度：12 mmBase Number Matches：1

XC95144XV-4CSG144I 数据手册

 浏览型号XC95144XV-4CSG144I的Datasheet PDF文件第2页浏览型号XC95144XV-4CSG144I的Datasheet PDF文件第3页浏览型号XC95144XV-4CSG144I的Datasheet PDF文件第4页浏览型号XC95144XV-4CSG144I的Datasheet PDF文件第5页浏览型号XC95144XV-4CSG144I的Datasheet PDF文件第6页浏览型号XC95144XV-4CSG144I的Datasheet PDF文件第7页 
0
R
XC95144XV High-Performance  
CPLD  
0
1
DS051 (v2.0) January 25, 2001  
Advance Product Specification  
Features  
Power Estimation  
•
144 macrocells with 3,200 usable gates  
Power dissipation in CPLDs can vary substantially depend-  
ing on the system frequency, design application and output  
loading. To help reduce power dissipation, each macrocell  
in a XC9500XV device may be configured for low-power  
mode (from the default high-performance mode). In addi-  
tion, unused product-terms and macrocells are automati-  
cally deactivated by the software to further conserve power.  
•
Available in small footprint packages  
-
-
-
100-pin TQFP (81 user I/O pins)  
144-pin TQFP (117 user I/O pins)  
144-pin CSP (117 user I/O pins)  
•
•
Optimized for high-performance 2.5V systems  
-
-
Low power operation  
Multi-voltage operation  
For a general estimate of I , the following equation may be  
CC  
used:  
Advanced system features  
I
(mA) = MC (0.5) + MC (0.3) + MC(0.0045 mA/MHz) f  
HP LP  
CC  
-
-
-
In-system programmable  
Two separate output banks  
Where:  
MC = Macrocells in high-performance (default) mode  
Superior pin-locking and routability with  
FastCONNECT II™ switch matrix  
Extra wide 54-input Function Blocks  
Up to 90 product-terms per macrocell with  
individual product-term allocation  
HP  
MC = Macrocells in low-power mode  
LP  
-
-
MC = Total number of macrocells used  
f = Clock frequency (MHz)  
-
Local clock inversion with three global and one  
product-term clocks  
Individual output enable per output pin  
Input hysteresis on all user and boundary-scan pin  
inputs  
This calculation is based on typical operating conditions  
using a pattern of 16-bit up/down counters in each Function  
-
-
Block with no output loading. The actual I  
value varies  
CC  
with the design application and should be verified during  
normal system operation.  
-
-
Bus-hold ciruitry on all user pin inputs  
Full IEEE Standard 1149.1 boundary-scan (JTAG)  
Figure 1 shows the above estimation in a graphical form.  
•
•
•
•
Fast concurrent programming  
200  
200 MHz  
Slew rate control on individual outputs  
Enhanced data security features  
Excellent quality and reliability  
150  
-
Endurance exceeding 10,000 program/erase  
cycles  
120 MHz  
100  
-
-
20 year data retention  
ESD protection exceeding 2,000V  
50  
Description  
The XC95144XV is a 2.5V CPLD targeted for high-perfor-  
mance, low-voltage applications in leading-edge communi-  
cations and computing systems. It is comprised of eight  
54V18 Function Blocks, providing 3,200 usable gates with  
propagation delays of 4 ns.  
0
80  
120  
200  
40  
160  
Clock Frequency (MHz)  
DS051_01_012501  
Figure 1: Typical I vs. Frequency for XC95144XV  
CC  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS051 (v2.0) January 25, 2001  
www.xilinx.com  
1
Advance Product Specification  
1-800-255-7778  
 
1234567...9

中文翻译

下载PDF

与XC95144XV-4CSG144I相关器件

型号 品牌 获取价格 描述 数据表
XC95144XV-4TQ100C XILINX

获取价格

 		High-Performance CPLD
XC95144XV-4TQ100I XILINX

获取价格

 		High-Performance CPLD
XC95144XV-4TQ144C XILINX

获取价格

 		High-Performance CPLD
XC95144XV-4TQ144I XILINX

获取价格

 		High-Performance CPLD
XC95144XV-4TQG100C XILINX

获取价格

 		Flash PLD, 4ns, PQFP100, PLASTIC, TQFP-100
XC95144XV-4TQG100I XILINX

获取价格

 		Flash PLD, 4ns, PQFP100, PLASTIC, TQFP-100
XC95144XV-4TQG144C XILINX

获取价格

 		Flash PLD, 4ns, PQFP144, PLASTIC, TQFP-144
XC95144XV-4TQG144I XILINX

获取价格

 		Flash PLD, 4ns, PQFP144, PLASTIC, TQFP-144
XC95144XV-5CS144C XILINX

获取价格

 		High-Performance CPLD
XC95144XV-5CS144I XILINX

获取价格

 		High-Performance CPLD

与XC95144XV-4CSG144I相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证