Datasheet > XC95144XLSERIES

XC95144XLSERIES

更新时间： 2024-01-25 12:33:34

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High Performance CPLD

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XC95144XLSERIES 数据手册

XC95144XL High Performance

CPLD

Preliminary Product Specification

November 13, 1998 (Version 1.2)

Features

Power Estimation

•

5 ns pin-to-pin logic delays

Power dissipation in CPLDs can very substantially depend-

ing on the system frequency, design application, and output

loading. To help reduce power dissipation, each macrocell

in a XC9500XL device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

System frequency up to 178 MHz

144 macrocells with 3,200 usable gates

Available in small footprint packages

100-pin TQFP (81 user I/O pins)

144-pin TQFP (117 user I/O pins)

144-pin CSP (117 user I/O pins)

•

Optimized for high-performance 3.3 V systems

For a general estimate of I , the following equation may

Low power operation

5 V tolerant I/O pins accept 5 V, 3.3 V, and 2.5 V

signals

be used:

I_CC(mA) = MC_HP(0.5) + MC_LP(0.3) + MC(0.0045 mA/MHz) f

3.3 V or 2.5 V output capability

Advanced 0.35 micron feature size CMOS

FastFLASH™ technology

Where:

MC = Macrocells in high-performance (default) mode

Advanced system features

MC = Macrocells in low-power mode

In-system programmable

MC = Total number of macrocells used

f = Clock frequency (MHz)

Superior pin-locking and routability with

FastCONNECT II™ switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with individual

product-term allocation

Local clock inversion with 3 global and one product-

term clocks

Individual output enable per output pin with local

inversion

Input hysteresis on all user and boundary-scan pin

inputs

Bus-hold ciruitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

This calculation is based on typical operating conditions

using a pattern of 16-bit up/down counters in each Function

Block with no output loading. The actual I

with the design application and should be verified during

normal system operation.

value varies

Figure 1 shows the above estimation in graphical form.

200

178 MHz

•

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

150

Performance

High

104 MHz

100

Endurance exceeding 10,000 program/erase cycles

20 year data retention

ESD protection exceeding 2,000 V

ower

Low

•

Pin-compatible with 5 V-core XC95144 device in the

100-pin TQFP package

150

Clock Frequency (MHz)

100

200

Description

X5898C

The XC95144XL is a 3.3 V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of eight

54V18 Function Blocks, providing 3,200 usable gates with

propagation delays of 5 ns. See Figure 2 for architecture

overview.

Figure 1: Typical I_ccvs. Frequency for XC95144XL

November 13, 1998 (Version 1.2)

12 3 4 5 6 7...9

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与XC95144XLSERIES相关器件

型号	品牌	获取价格	描述	数据表
XC95144XV	XILINX	获取价格	High-Performance CPLD
XC95144XV_07	XILINX	获取价格	High-Performance CPLD
XC95144XV-4CS144C	XILINX	获取价格	High-Performance CPLD
XC95144XV-4CS144I	XILINX	获取价格	High-Performance CPLD
XC95144XV-4CSG144C	XILINX	获取价格	Flash PLD, 4ns, PBGA144, PLASTIC, CSP-144
XC95144XV-4CSG144I	XILINX	获取价格	Flash PLD, 4ns, PBGA144, PLASTIC, CSP-144
XC95144XV-4TQ100C	XILINX	获取价格	High-Performance CPLD
XC95144XV-4TQ100I	XILINX	获取价格	High-Performance CPLD
XC95144XV-4TQ144C	XILINX	获取价格	High-Performance CPLD
XC95144XV-4TQ144I	XILINX	获取价格	High-Performance CPLD

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